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MPC8540 Datasheet(PDF) 304 Page - Freescale Semiconductor, Inc |
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MPC8540 Datasheet(HTML) 304 Page - Freescale Semiconductor, Inc |
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304 / 1302 page ![]() MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1 6-54 Freescale Semiconductor Core Register Summary 6.15.4 Performance Monitor Counter Registers (PMC0–PMC3, UPMC0–UPMC3) Table 6-42. PMLCb0–PMLCb3 Field Descriptions Bits Name Description 32–52 — Reserved, should be cleared. 53–55 THRESHMUL Threshold multiple 000 Threshold field is multiplied by 1 (PMLCbn[THRESHOLD] × 1) 001 Threshold field is multiplied by 2 (PMLCbn[THRESHOLD] × 2) 010 Threshold field is multiplied by 4 (PMLCbn[THRESHOLD] × 4) 011 Threshold field is multiplied by 8 (PMLCbn[THRESHOLD] × 8) 100 Threshold field is multiplied by 16 (PMLCbn[THRESHOLD] × 16) 101 Threshold field is multiplied by 32 (PMLCbn[THRESHOLD] × 32) 110 Threshold field is multiplied by 64 (PMLCbn[THRESHOLD] × 64) 111 Threshold field is multiplied by 128 (PMLCbn[THRESHOLD] × 128) 56–57 — Reserved, should be cleared. 58–63 THRESHOLD Threshold. Only events that exceed the threshold value are counted. Such events are implementation-dependent as are the dimension (for example duration in cycles) and granularity with which the value is interpreted. By varying the value, software can obtain a profile of the event characteristics subject to thresholding. For example, if PMC1 is configured to count cache misses that last longer than the threshold value, software can obtain the distribution of cache miss durations for a given program by monitoring the program repeatedly using a different threshold each time. 32 33 63 Field OV Counter value Reset All zeros R/W PMC0–PMC3: Supervisor R/W UPMC0–UPMC3: User read only PMR PMC0: PMR16, PMC1: PMR17, PMC2,: PMR18, PMC3: PMR19 UPMC0: PMR0, UPMC1: PMR1, UPMC2,: PMR2, UPMC3: PMR3 Figure 6-59. Performance Monitor Counter Registers (PMC0–PMC3), User Performance Monitor Counter Registers (UPMC0–UPMC3) Table 6-43. PMC0–PMC3 Field Descriptions Bits Name Description 32 OV Overflow. When this bit is set, it indicates this counter reaches its maximum value. 33–63 Counter value Indicates the number of occurrences of the specified event |
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