MPC8540 datasheet(296/1302 Pages) FREESCALE

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MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

6-46

Freescale Semiconductor

Core Register Summary

6.13.2 Debug Status Register (DBSR)

40–41

DAC12M Data address compare 1/2 mode

00 Exact address compare. DAC1 debug events can occur only if the address of the data storage

access is equal to the value specified in DAC1. DAC2 debug events can occur only if the

address of the data storage access is equal to the value specified in DAC2.

01 Address bit match. DAC1 and DAC2 debug events can occur only if the address of the data

storage access, ANDed with the contents of DAC2 are equal to the contents of DAC1, also

ANDed with the contents of DAC2.

If DAC1US

≠ DAC2US or DAC1ER ≠ DAC2ER, results are boundedly undefined.

10 Inclusive address range compare. DAC1 and DAC2 debug events can occur only if the

address of the data storage access is greater than or equal to the value specified in DAC1 and

less than the value specified in DAC2.

If DAC1US

≠ DAC2US or DAC1ER ≠ DAC2ER, results are boundedly undefined.

11 Exclusive address range compare. DAC1 and DAC2 debug events can occur only if the

address of the data storage access is less than the value specified in DAC1 or is greater than

or equal to the value specified in DAC2.

If DAC1US

≠ DAC2US or DAC1ER ≠ DAC2ER, results are boundedly undefined.

42–63

—

Reserved, should be cleared.

42 43

Field IDE UDE MRR ICMP BRT IRPT TRAP IAC1 IAC2

—

DAC1R DAC1W DAC2R DAC2W RET

—

Reset

Undef.

0000_0000_0000

R/W

SPR

SPR 304

Figure 6-51. Debug Status Register (DBSR)

Table 6-35. DBSR Field Descriptions

Bits

Name

Description

IDE

Imprecise debug event. Set if MSR[DE] = 0 and a debug event causes its respective DBSR bit to

be set. Functions as write-one-to-clear.

UDE

Unconditional debug event. Set if an unconditional debug event occurred. Functions as

write-one-to-clear. If UDE (level sensitive, active low) is asserted, DBSR[UDE] is affected as follows:

MSR[DE]DBCR0[IDM]Action

X 0 No action.

0 1 UDE is set.

1 1 UDE is set and a debug interrupt is taken.

34–35

MRR

Most recent reset. Functions as write-one-to-clear. Undefined at power-up. The e500 implements

HRESET as follows:

0x No hard reset occurred since this bit was last cleared by software.

1x The previous reset was a hard reset.

ICMP

Instruction complete debug event. Set if an instruction completion debug event occurred and

DBCR0[ICMP] = 1. Functions as write-one-to-clear.

Table 6-34. DBCR2 Field Descriptions (continued)

Bits

Name

Description

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