MPC8540 datasheet(293/1302 Pages) FREESCALE

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Debug Registers

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

Freescale Semiconductor

6-43

6.13.1.2 Debug Control Register 1 (DBCR1)

IAC1

Instruction address compare 1 debug event enable

0 IAC1 debug events cannot occur

1 IAC1 debug events can occur

IAC2

Instruction address compare 2 debug event enable

0 IAC2 debug events cannot occur

1 IAC2 debug events can occur

42–43

—

Reserved, should be cleared.

44–45

DAC1

Data address compare 1 debug event enable

00 DAC1 debug events cannot occur

01 DAC1 debug events can occur only if a store-type data storage access

10 DAC1 debug events can occur only if a load-type data storage access

11 DAC1 debug events can occur on any data storage access

46–47

DAC2

Data address compare 2 debug event enable

00 DAC2 debug events cannot occur

01 DAC2 debug events can occur only if a store-type data storage access

10 DAC2 debug events can occur only if a load-type data storage access

11 DAC2 debug events can occur on any data storage access

RET

Return debug event enable

0 RET debug events cannot occur

1 RET debug events can occur

Note: An rfci does not cause an RET debug event if MSR[DE] = 0 at the time that rfci executes.

49–62

—

Reserved, should be cleared.

Freeze timers on debug event

0 Enable clocking of timers

1 Disable clocking of timers if any DBSR bit is set (except MRR)

Field IAC1US IAC1ER IAC2US IAC2ER IAC12M

—

Reset

All zeros

R/W

SPR

SPR 309

Figure 6-49. Debug Control Register 1 (DBCR1)

Table 6-32. DBCR0 Field Descriptions (continued)

Bits

Name

Description

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