MPC8540 datasheet(291/1302 Pages) FREESCALE

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MMU Registers

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

Freescale Semiconductor

6-41

6.12.5.6 MAS Register 6 (MAS6)

46–47

TIDSELD

TID default selection value. A 2-bit field that specifies which of the current PID registers should be

used to load the MAS1[TID] field on a TLB miss exception.

The e500 implementation defines this field as follows:

00 PID0

01 PID1

10 PID2

11 TIDZ (0x00) (all zeros)

48–51

—

Reserved, should be cleared.

52–55

TSIZED

Default TSIZE value. Specifies the default value to be loaded into MAS1[TSIZE] on a TLB miss

exception.

—

Reserved, should be cleared.

X0D

Default X0 value. Specifies the default value to be loaded into MAS2[X0] on a TLB miss exception.

X1D

Default X1 value. Specifies the default value to be loaded into MAS2[X1] on a TLB miss exception.

Default W value. Specifies the default value to be loaded into MAS2[W] on a TLB miss exception.

Default I value. Specifies the default value to be loaded into MAS2[I] on a TLB miss exception.

Default M value. Specifies the default value to be loaded into MAS2[M] on a TLB miss exception.

Default G value. Specifies the default value to be loaded into MAS2[G] on a TLB miss exception.

Default E value. Specifies the default value to be loaded into MAS2[E] on a TLB miss exception.

39 40

47 48

Field

—

SPID0

—

SAS

Reset

All zeros

R/W

SPR

SPR 630

Figure 6-47. MAS Register 6 (MAS6)

Table 6-31. MAS6—TLB Search Context Register 0

Bits

Name

Comments, or Function when Set

32–39

—

Reserved, should be cleared.

40–47

SPID0

Specifies the PID value (recent value of PID0) used when searching the TLB during

execution of tlbsx.

48–62

—

Reserved, should be cleared.

SAS

Address space (AS) value for searches. Specifies the value of AS used when searching the

TLB (during execution of tlbsx).

Table 6-30. MAS4 Field Descriptions—Hardware Replacement Assist

Configuration (continued)

Bits

Name

Description

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