MPC8540 datasheet(288/1302 Pages) FREESCALE

288 / 1302 page

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

6-38

Freescale Semiconductor

Core Register Summary

6.12.5.2 MAS Register 1 (MAS1)

39 40

47 48

50 51

55 56

Field V IPROT

—

TID

—

TSIZE

—

Reset

All zeros

R/W

SPR

SPR 625

Figure 6-43. MAS Register 1 (MAS1)

Table 6-27. MAS1 Field Descriptions—Descriptor Context and Configuration

Control

Bits

Name

Descriptions

TLB valid bit

0 This TLB entry is invalid.

1 This TLB entry is valid.

IPRO

Invalidate protect. Set to protect this TLB entry from invalidate operations due the execution of tlbiva[x]

(TLB1 only). Note that not all TLB arrays are necessarily protected from invalidation with IPROT. Arrays

that support invalidate protection are denoted as such in the TLB configuration registers.

0 Entry is not protected from invalidation

1 Entry is protected from invalidation.

34–39

—

Reserved, should be cleared.

40–47

TID

Translation identity. An 8-bit field that defines the process ID for this TLB entry. TID is compared with

the current process IDs of the three virtual address to be translated. A TID value of 0 defines an entry

as global and matches with all process IDs.

48–50

—

Reserved, should be cleared.

Translation space. This bit is compared with the IS or DS fields of the MSR (depending on the type of

access) to determine if this TLB entry may be used for translation.

52–55 TSIZE Translation size. Defines the TLB entry page size. For arrays that contain fixed-size TLB entries, TSIZE

is ignored. For variable page size arrays, the page size is 4TSIZE Kbytes. Note that although the

Freescale Semiconductor Book E standard supports all 16 page sizes defined in Book E, the e500

supports only the following:

0001 4 Kbyte

0010 16 Kbyte

0011 64 Kbyte

0100 256 Kbyte

0101 1 Mbyte

0110 4 Mbyte

0111 16 Mbyte

1000 64 Mbyte

1001 256 Mbyte

56–63

—

Reserved, should be cleared.

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