MPC8540 datasheet(284/1302 Pages) FREESCALE

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MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

6-34

Freescale Semiconductor

Core Register Summary

6.12 MMU Registers

6.12.1 Process ID Registers (PID0–PID2)

6.12.2 MMU Control and Status Register 0 (MMUCSR0)

55 56

Field

—

Process ID

Reset

All zeros

R/W

SPR

Book E defined: SPR 48(PID0); EIS defined: SPR 633 (PID1); SPR 634 (PID2)

Figure 6-37. Process ID Registers (PID0–PID2)

Field

—

L2TLB0_FI

L2TLB1_FI

—

Reset

All zeros

R/W

SPR

SPR 1012

Figure 6-38. MMU Control and Status Register 0 (MMUCSR0)

Table 6-22. MMUCSR0 Field Descriptions

Bits

Name

Description

32–60

—

Reserved, should be cleared.

L2TLB0_FI

TLB0 flash invalidate (write to 1 to invalidate)

L2TLB1_FI

TLB1 flash invalidate (write 1 to invalidate)

0 No flash invalidate. Writing a 0 to this bit during an invalidation operation is ignored.

1 TLB1 invalidation operation. Hardware initiates a TLB1 invalidation operation.

When this operation is complete, this bit is cleared. Writing a 1 during an

invalidation operation causes an undefined operation.

—

Reserved, should be cleared.

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