MPC8540 datasheet(282/1302 Pages) FREESCALE

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MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

6-32

Freescale Semiconductor

Core Register Summary

6.11.3 L1 Cache Configuration Register 0 (L1CFG0)

ICLO Instruction cache lock overflow. Sticky bit set by hardware and cleared by writing 0 to this bit location.

0 Indicates a lock overflow condition was not encountered in the instruction cache

1 Indicates a lock overflow condition was encountered in the instruction cache

ICLF

Instruction cache lock bits flash reset. Writing 0 and then 1 flash clears the lock bit of all entries in the

instruction cache; clearing occurs independently from the value of the enable bit (ICE). ICLFR is always read

as 0.

56–61

—

Reserved, should be cleared.

ICFI

Instruction cache flash invalidate. Written to 0 and then 1 to flash clear the valid bit of all entries in the

instruction cache; operates independently from the value of the enable bit (ICE). ICI is always read as 0.

ICE

Instruction cache enable

0 The instruction cache is neither accessed or updated.

1 Enables instruction cache operation

49 50

Field CARCH

—

CBSIZE CREPL CLA CPA

—

CNWAY

—

CSIZE

Reset

00_000

000_00

11_1

000

0010_0000

R/W

Read only

SPR

SPR 515

Figure 6-35. L1 Cache Configuration Register 0 (L1CFG0)

Table 6-20. L1CFG0 Field Descriptions

Bits

Name

Description

32–33

CARCH

Cache architecture

00 Harvard

01 Unified

34–38

—

Reserved, should be cleared.

39–40

CBSIZE

Cache line size

0 32 bytes

1 64 bytes

41–42

CREPL

Cache replacement policy

0 True LRU

1 Pseudo LRU

CLA

Cache locking APU available

0 Unavailable

1Available

Table 6-19. L1CSR1 Field Descriptions (continued)

Bits

Name

Description

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