MPC8540 datasheet(280/1302 Pages) FREESCALE

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MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

6-30

Freescale Semiconductor

Core Register Summary

6.11 L1 Cache Configuration Registers

6.11.1 L1 Cache Control and Status Register 0 (L1CSR0)

Line Locking APU Bits

49 51

Field

—

CPE CPI

—

CSLC CUL CLO CLFR

—

CFI CE

Reset

All zeros

R/W

SPR

SPR 1010

Figure 6-33. L1 Cache Control and Status Register 0 (L1CSR0)

Table 6-18. L1CSR0 Field Descriptions

Bits

Nam

Description

32–46

—

Reserved, should be cleared.

CPE

(Data) Cache parity enable

0 Parity checking of the cache disabled

1 Parity checking of the cache enabled

CPI

(Data) Parity error injection enable

0 Parity error injection disabled

1 Parity error injection enabled. Cache parity must also be enabled (CPE = 1) when this bit is set.

49–51

—

Reserved, should be cleared.

CSL

(Data) Cache snoop lock clear. Sticky bit set by hardware if a dcbi snoop (either internally or externally

generated) invalidated a locked cache line. Note that the lock bit for that line is cleared whenever the line is

invalidated. This bit can be cleared only by software.

0 The cache has not encountered an dcbi snoop that invalidated a locked line.

1 The cache has encountered an dcbi snoop that invalidated a locked line.

CUL

(Data) Cache unable to lock. Sticky bit set by hardware and cleared by writing 0 to this bit location.

0 Indicates a lock set instruction was effective in the cache

1 Indicates a lock set instruction was not effective in the cache

CLO

(Data) Cache lock overflow. Sticky bit set by hardware and cleared by writing 0 to this bit location.

0 Indicates a lock overflow condition was not encountered in the cache

1 Indicates a lock overflow condition was encountered in the cache

CLF

(Data) Cache lock bits flash reset. Writing a 1 during a flash clear operation causes an undefined operation.

Writing a 0 during a flash clear operation is ignored. Clearing occurs regardless of the enable (CE) value.

0 Default.

1 Hardware initiates a cache lock bits flash clear operation. This bit is cleared when the operation is complete.

56–61

—

Reserved, should be cleared.

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