MPC8540 datasheet(278/1302 Pages) FREESCALE

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MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

6-28

Freescale Semiconductor

Core Register Summary

6.10.2 Hardware Implementation-Dependent Register 1 (HID1)

51–62

—

Reserved, should be cleared.

NOPTI

No-op the data and instruction cache touch instructions.

0 dcbt, dcbtst, and icbt are enabled, as defined by the EIS. On the e500, if CT = 0, icbt is always a

no-op, regardless of the value of NOPTI. If CT = 1, icbt does a touch load to an L2 cache, if one is

present.

1 dcbt, dcbtst, and icbt are treated as no-ops; dcblc and dcbtls are not.

Field PLL_MODE PLL_CFG

—

RFXE

—

ASTME ABE

—

Reset

01[PLL_CFG]_0000_0000_0000_0000_0000_0000

R/W

SPR

SPR 1009

Figure 6-32. Hardware Implementation-Dependent Register 1 (HID1)

Table 6-17. HID1 Field Descriptions

Bits

Name

Description

32–33

PLL_MOD

Read-only for integrated devices.

01 Fixed value for MPC8540

34–39

PLL_CFG

Reflected directly from configuration input pins (read-only). PLL_CFG[0–4] corresponds to the integer

divide ratio and PLL_CFG5 is the half-mode bit. MPC8540 supports the following:

00010 0 ratio of 2:1

00010 1 ratio of 5:2 (2.5:1)

00011 0 ratio of 3:1

00011 1 ratio of 7:2 (3.5:1)

Note that this value is also reflected to PORPLLSR[e500_Ratio]. See Section 18.4.1.1, “POR PLL Status

40–45

—

Reserved, should be cleared.

Table 6-16. HID0 Field Descriptions (continued)

Bits

Name

Description

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