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MPC8540 Datasheet(PDF) 274 Page - Freescale Semiconductor, Inc |
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MPC8540 Datasheet(HTML) 274 Page - Freescale Semiconductor, Inc |
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274 / 1302 page  MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1 6-24 Freescale Semiconductor Core Register Summary 6.8 Software-Use SPRs (SPRG0–SPRG7 and USPRG0) 48–55 — Reserved, should be cleared. — 56 BUS_IAERR Bus instruction address error Maybe 57 BUS_RAERR Bus read address error Maybe 58 BUS_WAERR Bus write address error Maybe 59 BUS_IBERR Bus instruction data bus error Maybe 60 BUS_RBERR Bus read data bus error Maybe 61 BUS_WBERR Bus write bus error Maybe 62 BUS_IPERR Bus instruction parity error Maybe 63 BUS_RPERR Bus read parity error Maybe 32 63 Field Software-determined information Reset All zeros SPR R/W SPRG0 272 Read/Write Supervisor SPRG1 273 Read/Write Supervisor SPRG2 274 Read/Write Supervisor SPRG3 259 Read-only User/Supervisor 275 Read/Write Supervisor SPRG4 260 Read-only User/Supervisor 276 Read/Write Supervisor SPRG5 261 Read-only User/Supervisor 277 Read/Write Supervisor SPRG6 262 Read-only User/Supervisor 278 Read/Write Supervisor SPRG7 263 Read-only User/Supervisor 279 Read/Write Supervisor USPRG0 256 Read/Write User/Supervisor Figure 6-27. Software-Use SPRs (SPRG0–SPRG7 and USPRG0) Table 6-12. MCSR Field Descriptions (continued) Bit Name Description Recoverable |
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