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Interrupt Registers

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

Freescale Semiconductor

6-21

6.7.2

EIS-Defined Interrupt Registers

6.7.2.1

Machine Check Save/Restore Register 0 (MCSRR0)

Table 6-11. ESR Field Descriptions

Bits

Name

Syndrome

Interrupt Types

32–35

—

Reserved, should be cleared. (Defined by Book E as allocated.)

—

PIL

Illegal instruction exception

Program

PPR

Privileged instruction exception

Program

PTR

Trap exception

Program

—

Defined by Book E for floating-point operations. Reserved and permanently

cleared because the e500 does not implement a Book E FPU. Setting it has

no effect.

—

Store operation

Alignment, data

storage, data TLB

error

—

Reserved, should be cleared.

—

DLK

Cache locking. Settings are implementation-dependent.

0 Default

1 On the e500, DLK is set when a DSI occurs because dcbtls, dcbtstls, or

dcblc is executed in user mode while MSR[UCLE] = 0.

Data storage

ILK

Set when a DSI occurs because icbtl or icblc is executed in user mode

(MSR[PR] = 1) and MSR[UCLE] = 0

Data storage

44–45

—

Reserved, should be cleared.

Byte-ordering exception

Data storage,

instruction storage

47–55

—

Reserved, should be cleared.

—

SPE

SPE exception bit (e500-specific)

0 Default

1 Any exception caused by an SPE or SPFP instruction

SPE unavailable

57–63

—

Reserved, should be cleared. (Defined by Book E as allocated.)

—

Field

Next instruction address

Reset

All zeros

R/W

SPR

SPR 570

Figure 6-23. Machine Check Save/Restore Register 0 (MCSRR0)

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