MPC8540 datasheet(273/1302 Pages) FREESCALE

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Interrupt Registers

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

Freescale Semiconductor

6-23

6.7.2.4

Machine Check Syndrome Register (MCSR)

Field

MCP

ICPERR

DCP_PERR

DCPERR

—

Reset

All zeros

R/W

Field

—

GL_CI

Reset

All zeros

R/W

Field

—

Reset

All zeros

R/W

Field BUS_IAERR BUS_RAERR BUS_WAERR BUS_IBERR BUS_RBERR BUS_WBERR BUS_IPERR BUS_RPERR

Reset

All zeros

R/W

SPR

SPR 572

Figure 6-26. Machine Check Syndrome Register (MCSR)

Table 6-12. MCSR Field Descriptions

Bit

Name

Description

Recoverable

MCP

Machine check input pin

Maybe

ICPERR

Instruction cache parity error

Precise

DCP_PERR

Data cache push parity error

Maybe

DCPERR

Data cache parity error

Precise. (Cache-inhibited stwcx. instructions and guarded

loads that initiate this error are deallocated before a

machine check is taken. MCSRR0 holds the address of the

next instruction, not the instruction that initiated the error.)

36–46

—

Reserved, should be cleared.

—

GL_CI

Set when a guarded load or

cache-inhibited stwcx. causes

a cache parity error (ICPERR,

DCPERR)—MCSRR0 holds

the address for the instruction

after the instruction that

caused the error.

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