MPC8540 datasheet(276/1302 Pages) FREESCALE

276 / 1302 page

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

6-26

Freescale Semiconductor

Core Register Summary

6.9.3

Branch Unit Control and Status Register (BUCSR)

IAB2

Instruction after branch bit 2 (with BBEAR[62–63]). IAB is a 3-bit pointer that points to the

instruction in the cache line after the branch. See the description for bblels in the EREF. If the

branch is the last instruction in the cache block, IAB = 000, to indicate the next sequential

instruction, which resides in the zeroth position of the next cache block.

BDIRPR

Branch direction prediction. The user can pick the direction of the predicted branch.

0 The locked address is always predicted as not taken.

1 The locked address is always predicted as taken.

Field

—

BBFI BBLO BBUL BBLFC

—

BPEN

Reset

All zeros

R/W

SPR

SPR 1013

Figure 6-30. Branch Unit Control and Status Register (BUCSR)

Table 6-15. BUCSR Field Descriptions

Bits

Name

Description

32–5

—

Reserved, should be cleared.

BBFI

Branch buffer flash invalidate. Clearing and then setting BBFI flash clears the valid bit of all entries in

the branch buffer; clearing occurs independently from the value of the enable bit (BPEN). BBFI is

always read as 0.

BBLO Branch buffer lock overflow status

0 Indicates a lock overflow condition was not encountered in the branch buffer

1 Indicates a lock overflow condition was encountered in the branch buffer

This sticky bit is set by hardware and is cleared by writing 0 to this bit location.

BBUL

Branch buffer unable to lock

0 Indicates a lock overflow condition in the branch buffer

1 Indicates a lock set instruction failed in the branch buffer, for example, if the BTB is disabled.

This sticky bit is set by hardware and is cleared by writing 0 to this bit location.

BBLF

Branch buffer lock bits flash clear. Clearing and then setting BBLFC flash clears the lock bit of all

entries in the branch buffer; clearing occurs independently from the value of the enable bit (BPEN).

BBLFC is always read as 0.

58–6

—

Reserved, should be cleared.

BPEN Branch prediction enable

0 Branch prediction disabled

1 Branch prediction enabled (enables BTB to predict branches)

Table 6-14. BBTAR Field Descriptions (continued)

Bits

Name

Description

MPC8540 Datasheet(PDF) 276 Page - Freescale Semiconductor, Inc

MPC8540 Datasheet(HTML) 276 Page - Freescale Semiconductor, Inc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL