MPC8540 datasheet(279/1302 Pages) FREESCALE

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Hardware Implementation-Dependent Registers

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

Freescale Semiconductor

6-29

RFXE

Read fault exception enable. Controls whether assertion of core_fault_in causes a machine check

interrupt. The assertion of core_fault_in can result from an L2 multibit ECC error. It can also occur for a

system error if logic on the integrated device signals a fault for nonfatal errors (read data is corrupt (or

zero), but the bus transaction can complete without corrupting other system state, making it unnecessary

to take a machine check (for example, a master abort of a PCI transaction).

0 Assertion of core_fault_in cannot cause a machine check. RFXE should be left clear if an interrupt is

to be reported by the integrated device through int or c_int for this condition. If RFXE = 0, it is important

that the integrated device generates an interrupt if core_fault_in is asserted.

If core_fault_in is asserted, any data on the CCB is dropped, stalling the load/store unit and eventually

causing the e500 pipeline either to stall until an interrupt occurs (typically generated by the

programmable interrupt controller (PIC) in response to the fault) or to continue processing with bad

data untill the interrupt occurs. Because core_fault_in cannot cause a machine check, if RFXE is 0, it

is critical that the system be configured to generate the appropriate interrupt.

It is also possible to hang the processor (requiring a hard reset to recover) if a guarded load hits in the

L2 cache and gets an uncorrectable ECC error. Because of this, avoid defining memory as cacheable

but guarded. If this combination is required, RFXE must be enabled, in which case an error causes

both a machine check interrupt and an external interrupt when a bus fault condition is detected unless

interrupts are masked for all sources of bus faults, such as DRAM ECC errors, PCI parity errors, local

bus parity errors, and others.

RFXE must also be set if software requires that code execution stop immediately when a bus fault

occurs rather than continuing with the bad data until the interrupt arrives. Again, this results in both a

machine check interrupt and an external interrupt when a bus fault is detected, unless all possible

sources for bus fault have their interrupts masked.þThe machine check interrupt can then reenable

normal interrupts and wait for the interrupt due to the fault to be received before returning from the

machine check.

1 A machine check can occur due to assertion of core_fault_in.

If MSR[ME] = 1 and a fault is signaled, a machine check interrupt occurs.

If MSR[ME] = 0 and a fault is signaled, a checkstop occurs.

Note that if RFXE is set and another mechanism is configured to generate an interrupt in response to

assertion of core_fault_in, the same event causes two interrupts, the machine check enabled by setting

RFXE and the interrupt triggered by the on-chip peripheral or other block; therefore, RFXE should be

set only if no other mechanism is configured to generate an interrupt for this case.

Note that the L2 cache detects any assertion of core_fault_in and ensures that the L2 cache is not

corrupted when data is dropped for this type of transaction.

47–49

—

Reserved, should be cleared.

ASTME

Address bus streaming mode enable. This bit, along with the ECM stream control bits in the EEBACR,

enables address bus streaming on the CCB. See Section 8.2.1.1, “ECM CCB Address Configuration

0 Address bus streaming mode disabled

1 Address bus streaming mode enabled

ABE

Address broadcast enable. The e500 broadcasts cache management instructions (dcbst, dcblc

(CT = 1), icblc (CT = 1), dcbf, dcbi, mbar, msync, tlbsync, icbi) based on ABE. On the MPC8540

, ABE

must be set to allow management of external L2 caches.

0 Address broadcasting disabled

1 Address broadcasting enabled

52–63

—

Reserved, should be cleared.

Table 6-17. HID1 Field Descriptions (continued)

Bits

Name

Description

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