MPC8540 datasheet(281/1302 Pages) FREESCALE

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L1 Cache Configuration Registers

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

Freescale Semiconductor

6-31

6.11.2 L1 Cache Control and Status Register 1 (L1CSR1)

CFI

(Data) Cache flash invalidate.

0 No cache invalidate. Writing a 0 to CFI during an invalidation operation is ignored.

1 Cache invalidation operation. A cache invalidation operation is initiated by hardware. Once complete, this bit

is cleared. Writing a 1 during an invalidation operation causes an undefined operation.

Invalidation occurs regardless of the enable (CE) value.

(Data) Cache enable

0 The cache is neither accessed or updated.

1 Enables cache operation

Line Locking APU Bits

Field

—

ICPE

ICPI

—

ICSLC

ICUL

ICLO

ICLFR

—

ICFI ICE

Reset

All zeros

R/W

SPR

SPR 1011

Figure 6-34. L1 Cache Control and Status Register 1 (L1CSR1)

Table 6-19. L1CSR1 Field Descriptions

Bits

Name

Description

32–46

—

Reserved, should be cleared.

ICPE Instruction cache parity enable

0 Parity checking of the instruction cache disabled

1 Parity checking of the instruction cache enabled

ICPI

Instruction parity error injection enable

0 Parity error injection disabled

1 Parity error injection enabled. Note that instruction cache parity must also be enabled (ICPE = 1) when this

bit is set.

49–51

—

Reserved, should be cleared.

ICSL

Instruction cache snoop lock clear. Sticky bit set by hardware if an icbi snoop (either internally or externally

generated) invalidated a locked line in the instruction cache. Note that the lock bit for that line is cleared

whenever the line is invalidated. This bit can only be cleared by software.

0 The instruction cache has not encountered an icbi snoop that invalidated a locked line.

1 The instruction cache has encountered an icbi snoop that invalidated a locked line.

ICUL Instruction cache unable to lock. Sticky bit set by hardware and cleared by writing 0 to this bit location.

0 Indicates a lock set instruction was effective in the instruction cache

1 Indicates a lock set instruction was not effective in the instruction cache

Table 6-18. L1CSR0 Field Descriptions (continued)

Bits

Nam

Description

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