MPC8540 datasheet(283/1302 Pages) FREESCALE

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L1 Cache Configuration Registers

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

Freescale Semiconductor

6-33

6.11.4 L1 Cache Configuration Register 1 (L1CFG1)

CPA

Cache parity available

0 Unavailable

1Available

45–49

—

Reserved, should be cleared.

50–52

CNWAY

Cache number of ways

111 Indicates 8 ways

53–55

—

Reserved, should be cleared.

56–63

CSIZE

Cache size

0x20 indicates 32 Kbytes

Field

—

ICBSIZ

ICREPL ICLA ICP

ICNWAY

ICSIZE

Reset

0000_000

0_0

000_0011_1

000_0010_0000

R/W

Read only

SPR

SPR 516

Figure 6-36. L1 Cache Configuration Register 1 (L1CFG1)

Table 6-21. L1CFG1 Field Descriptions

Bits

Name

Description

32–38

—

Reserved, should be cleared.

39–40

ICBSIZ

Instruction cache block size

00 Indicates block size of 32 bytes

41–42

ICREPL Instruction cache replacement policy

01 Indicates pseudo-LRU policy

ICLA

Instruction cache locking available

1 Indicates available

ICPA

Instruction cache parity available

1 Indicates available

45–52

ICNWAY Instruction cache number of ways

111 Indicates 8 ways

53–63

ICSIZE

Instruction cache size

0x20 indicates 32 Kbytes

Table 6-20. L1CFG0 Field Descriptions (continued)

Bits

Name

Description

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