MPC8540 datasheet(289/1302 Pages) FREESCALE

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MMU Registers

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

Freescale Semiconductor

6-39

6.12.5.3 MAS Register 2 (MAS2)

51 52

56 57

58 59 60 61 62 63

Field

EPN

—

X0 X1 W I M G E

Reset

All zeros

R/W

SPR

SPR 626

Figure 6-44. MAS Register 2 (MAS2)

Table 6-28. MAS2 Field Descriptions—EPN and Page Attributes

Bits

Name

Description

32–5

EPN

Effective page number. Depending on page size, only the bits associated with a page boundary are

valid. Bits that represent offsets within a page are ignored and should be cleared.

52–5

—

Reserved for implementation-specific use

Implementation-dependent page attribute

Write-through

0 This page is considered write-back with respect to the caches in the system.

1 All stores performed to this page are written through the caches to main memory.

Caching-inhibited

0 Accesses to this page are considered cacheable.

1 The page is considered caching-inhibited. All loads and stores to the page bypass the caches

and are performed directly to main memory.

Memory coherence required

0 Memory coherence is not required.

1 Memory coherence is required. This allows loads and stores to this page to be coherent with

loads and stores from other processors (and devices) in the system, assuming all such devices

are participating in the coherence protocol.

Guarded

0 Accesses to this page are not guarded and can be performed before it is known if they are

required by the sequential execution model.

1 All loads and stores to this page that miss in the L1 cache are performed without speculation (that

is, they are known to be required). Speculative loads can be performed if they hit in the L1 cache.

In addition, accesses to caching-inhibited pages are performed using only the memory element

that is explicitly specified.

Endianness. Determines endianness for the corresponding page. Little-endian operation is true little

endian, which differs from the modified little-endian byte-ordering model optionally available in

previous devices that implement the original PowerPC architecture. See the e500 Reference

Manual for more information on the Book E definition of endianness.

0 The page is accessed in big-endian byte order.

1 The page is accessed in true little-endian byte order.

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