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AT88SC1003 Datasheet(PDF) 21 Page - ATMEL Corporation |
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AT88SC1003 Datasheet(HTML) 21 Page - ATMEL Corporation |
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21 / 30 page  21 AT88SC1003 2035B–SMEM–08/03 Figure 5. Inc/Read Note: PGM and RST must both be low during a read cycle. I/O should not be driven (except by the external pullup resistor). Figure 6. Erase/Write Note: During any erase or write operation, PGM must fall before the falling edge of CLK at the end of t CHP (recommend a minimum setup time of 1 usec). After the rising edge of PGM to initiate the erase/write operation, delay at least t DV (2 usec) before driving data on the I/O contact. Address CLK I/O t DV t CL t CH t CLK t OH t OH Address CLK t OH PGM Output Input t DV Valid Valid tSPR tHPR tCHP tDS t DH An An An An-1 An+1 Drive "1" (Erase) or "0" (Write) I/O Read Erase/Write Read t DV Output |
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