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TDA7569LVPD Datasheet(PDF) 27 Page - STMicroelectronics |
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TDA7569LVPD Datasheet(HTML) 27 Page - STMicroelectronics |
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27 / 39 page ![]() TDA7569LV I2C bus Doc ID 018712 Rev 3 27/39 8.3.2 Start and stop conditions As shown by Figure 37 a start condition is a HIGH to LOW transition of the SDA line while SCL is HIGH. The stop condition is a LOW to HIGH transition of the SDA line while SCL is HIGH. 8.3.3 Byte format Every byte transferred to the SDA line must contain 8 bits. Each byte must be followed by an acknowledge bit. The MSB is transferred first. 8.3.4 Acknowledge The transmitter* puts a resistive HIGH level on the SDA line during the acknowledge clock pulse (see Figure 38). The receiver** the acknowledges has to pull-down (LOW) the SDA line during the acknowledge clock pulse, so that the SDA line is stable LOW during this clock pulse. * Transmitter –master ( μP) when it writes an address to the TDA7569LV – slave (TDA7569LV) when the μP reads a data byte from TDA7569LV ** Receiver – slave (TDA7569LV) when the μP writes an address to the TDA7569LV – master (µP) when it reads a data byte from TDA7569LV Figure 36. Data validity on the I2C bus Figure 37. Timing diagram on the I2C bus Figure 38. Acknowledge on the I2C bus |
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