DF2B6M4BSL

2

4. Packaging

SL2

5. Example of Circuit Diagram

Fig. 5.1

High frequency antenna circuit

Fig. 5.2

High-speed signal circuit

6. Quick Reference Data

Characteristics

Working peak reverse voltage

Total capacitance

Dynamic resistance

Electrostatic discharge voltage

(IEC61000-4-2) (Contact)

Symbol

VRWM

Ct

RDYN

VESD

Note

(Note 1)

(Note 2)

(Note 3)

Test Condition

�

VR = 0 V, f = 1 MHz

�

�

Min

�

�

�

8

Typ.

�

0.12

1.05

�

Max

5.5

0.15

�

�

Unit

V

pF

Ω

kV

Note 1: Recommended operating condition.

Note 2: TLP parameters: Z0 = 50 Ω, tp = 100 ns, tr = 300 ps, averaging window: t1 = 30 ns to t2 = 60 ns, extraction of

dynamic resistance using least squares fit of TLP characteristics between IPP1 = 8 A and IPP2 = 16 A.

Note 3: Criterion: No damage to devices.

2021-12-02

Rev.1.0

©2021

Toshiba Electronic Devices & Storage Corporation