6

ICS93701

0417B—10/29/02

Switching Characteristics

PARAMETER

SYMBOL

CONDITION

MIN

TYP

MAX

UNITS

Low-to high level

propagation delay time

High-to low level

propagation delay time

Output enable time

PD# to any output

3

ns

Output disable time

tdis

PD# to any output

3

ns

Period Jitter

100/133/166MHz

-40

±25

40

ps

Half-period jitter

t(jit_hper)

100/133/166MHz

-120

±50

100

ps

Cycle to Cycle Jitter1

100/133/166MHz

30

65

ps

Phase error

100/133/166Mhz

-150

-100

150

ps

Output to Output Skew

60

100

ps

Pulse skew

60

100

ps

66MHz to 100MHz

49.5

50

50.5

%

101MHz to 133MHz

48.5

49

50

%

135MHz to 167MHz

48.5

49

50

%

Slew Rate

Load = 120

Ω/14pF

11.9

2

ps

Notes:

1. Refers to transition on noninverting outputs in PLL bypass mode.

2. While the pulse skew is almost constant over frequency, the duty cycle error increases at

decreases as the frequency goes up.

Duty cycle

DC

2

3.5

1

CLK_IN to any output

3.5

1

CLK_IN to any output

ns

ns