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VLSI
Solution
y
VS1002d
VS1002D
7. SPI BUSES
7.7
SPI Examples with SM SDINEW and SM SDISHARED set
7.7.1
Two SCI Writes
0
1
2
3
30
31
1
0
1
0
0
0
0
0
0
0
X
X
XCS
SCK
SI
2
32
33
61
62
63
SCI Write 1
SCI Write 2
Figure 9: Two SCI Operations.
Figure 9 shows two consecutive SCI operations. Note that xCS must be raised to inactive state between
the writes.
7.7.2
Two SDI Bytes
1
2
3
XCS
SCK
SI
7
6
5
4
3
1
0
7
6
5
2
1
0
X
SDI Byte 1
SDI Byte 2
0
6
7
8
9
13
14
15
Figure 10: Two SDI Bytes.
SDI data is synchronized with a raising edge of xCS as shown in Figure 10. However, every byte doesn’t
need separate synchronization.
7.7.3
SCI Operation in Middle of Two SDI Bytes
0
1
XCS
SCK
SI
6
7
7
6
5
1
0
0
0
1
0
7
6
5
1
0
SDI Byte
SCI Operation
SDI Byte
8
9
38
39
40
41
46
47
X
Figure 11: Two SDI Bytes Separated By an SCI Operation.
Figure 11 shows how an SCI operation is embedded in between SDI operations. The changes in xCS are
used to synchronize both SDI and SCI.
Version 1.0,
2005-04-27
21
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