PRELIMINAR

Y

MAXIMUM RATINGS (TA=25°C)

SYMBOL

UNITS

Drain-Source Voltage

VDS

50

V

Drain-Gate Voltage

VDG

50

V

Gate-Source Voltage

VGS

40

V

Continuous Drain Current

ID

300

mA

Maximum Pulsed Drain Current

IDM

1.2

A

Power Dissipation

PD

350

mW (Note 1)

Power Dissipation

PD

300

mW (Note 2)

Power Dissipation

PD

150

mW (Note 3)

Operating and Storage

Junction Temperature

TJ,Tstg

-65 to +150

°C

Thermal Resistance

ΘJA

357

°C/W

ELECTRICAL CHARACTERISTICS PER TRANSISTOR (TA=25°C unless otherwise noted)

SYMBOL

TEST CONDITIONS

MIN

TYP

MAX

UNITS

IGSSF, IGSSR

VGS=5V

50

nA

IGSSF, IGSSR

VGS=10V

500

nA

IGSSF, IGSSR

VGS=12V

1.0

µA

IDSS

VDS=50V, VGS=0V

50

nA

BVDSS

VGS=0V, ID=10µA

50

V

VGS(th)

VDS=VGS, ID=250µA

0.5

1.2

V

rDS(ON)

VGS=1.8V, ID=50mA

1.6

2.3

Ω

rDS(ON)

VGS=2.5V, ID=50mA

1.3

1.9

Ω

rDS(ON)

VGS=5.0V, ID=50mA

1.1

1.5

Ω

gFS

VDS=10V, ID=200mA

200

mmhos

Crss

VDS=25V, VGS=0, f=1.0MHz

TBD

pF

Ciss

VDS=25V, VGS=0, f=1.0MHz

TBD

pF

Coss

VDS=25V, VGS=0, f=1.0MHz

TBD

pF

VSD

VGS=0V, IS=115mA

1.4

V

CMLDM7003

CMLDM7003J

DUAL N-CHANNEL

ENHANCEMENT-MODE

SILICON MOSFET

SOT-563 CASE

Central

Semiconductor Corp.

TM

R0 (26-June 2006)

DESCRIPTION:

The CENTRAL SEMICONDUCTOR CMLDM7003 and

CMLDM7003J are Enhancement-mode N-Channel Field

Effect Transistors, manufactured by the N-Channel

DMOS Process, designed for high speed pulsed amplifier

and driver applications. The CMLDM7003 utilizes the

USA pinout configuration, while the CMLDM7003J utilizes

the Japanese pinout configuration. These special Dual

Transistor devices offer low drain-source on state

resistance (rDS(ON)).

MARKING CODE: CMLDM7003:

C30

CMLDM7003J:

C3J