Central

Semiconductor Corp.

TM

SOT-563 CASE - MECHANICAL OUTLINE

CMLDM8002A

CMLDM8002AJ

SURFACE MOUNT PICOmini

TM

DUAL P-CHANNEL

ENHANCEMENT-MODE

SILICON MOSFET

R0 (24-January 2006)

LEAD CODE:

1) GATE Q1

2) SOURCE Q1

3) DRAIN Q2

4) GATE Q2

5) SOURCE Q2

6) DRAIN Q1

MARKING CODE: C08

LEAD CODE:

1) SOURCE Q1

2) GATE Q1

3) DRAIN Q2

4) SOURCE Q2

5) GATE Q2

6) DRAIN Q1

MARKING CODE: CJ8

ELECTRICAL CHARACTERISTICS PER TRANSISTOR - Continued (TA=25°C unless otherwise noted)

SYMBOL

TEST CONDITIONS

MIN

MAX

UNITS

VGS(th)

VDS=VGS, ID=250µA

1.0

2.5

V

VDS(ON)

VGS=10V, ID=500mA

1.5

V

VDS(ON)

VGS=5.0V, ID=50mA

0.15

V

rDS(ON)

VGS=10V, ID=500mA

2.5

Ω

rDS(ON)

VGS=10V, ID=500mA, Tj=125°C

4.0

Ω

rDS(ON)

VGS=5.0V, ID=50mA

3.0

Ω

rDS(ON)

VGS=5.0V, ID=50mA, Tj=125°C

5.0

Ω

Yfs

VDS =10V, ID=200mA

200

msec

Crss

VDS=25V, VGS=0, f=1.0MHz

7.0

pF

Ciss

VDS=25V, VGS=0, f=1.0MHz

70

pF

Coss

VDS=25V, VGS=0, f=1.0MHz

15

pF

ton

VDD=30V, VGS=10V, ID=200mA,

20

ns

toff

RG=25Ω, RL=150Ω

20

ns

VSD

VGS=0V, IS=115mA

1.3

V