| Electronic Components Datasheet Search |
|
FT903Q-R Datasheet(PDF) 50 Page - Bridgetek Pte Ltd. |
|
|
|||||||||||||||||||||||||||||
FT903Q-R Datasheet(HTML) 50 Page - Bridgetek Pte Ltd. |
|
50 / 67 page ![]() Copyright © Bridgetek Pte Ltd 50 FT900 /1/2/3 Revision C Embedded Microcontroller Datasheet Version 1.0 Document No. BRT_000172 Clearance No.: BRT#087 SD Host I/O pins dynamic characteristics for 25 MHz (Vcc (I/O) = 3.3V) Parameter Description Conditions Min Max Unit TSCLK clock period on pin SD_CLK 40 - ns TISU data input setup time 5 - ns TIH data input hold time 5 - ns TZO data output valid delay time 0 14 ns TOZ data output hold time 2.5 - ns Table 5-17 - SD Host I/O pins (SD_CLK, SD_CMD, SD_DATA3/DATA2/DATA1/DATA0, SD_CD, SD_WP) characteristics for 25 MHz SD Host I/O pins dynamic characteristics for 50 MHz (Vcc (I/O) = 3.3V) Parameter Description Conditions Min Max Unit TSCLK clock period on pin SD_CLK 18 - ns TISU data input setup time 6 - ns TIH data input hold time 2 - ns TZO data output valid delay time - 14 ns TOZ data output hold time 2.5 - ns Table 5-18 - SD Host I/O pins (SD_CLK, SD_CMD, SD_DATA3/DATA2/DATA1/DATA0, SD_CD, SD_WP) characteristics for 50 MHz Figure 5-11 - Definition of SD Host Timing |
|
Link URL |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link to Datasheet | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |