LCS7260C datasheet(13/35 Pages) POWERINT

13 / 35 page

Rev. D 11/22

HiperLCS-2

www.power.com

Isolation

Barrier

Device

Most

Sensitive

Returned to

Recommended

Value

Notes

Secondary Control

Secondary LSR2000

GSA

499 ohm

Switch signal hence pay attention to layout/coupling.

Secondary LSR2000

GSA

499 ohm

Switch signal hence pay attention to layout/coupling.

Secondary LSR2000

GSA

4.7 ohm

High current gate-drive. Wider PC-board trace to

limit inductance.

Secondary LSR2000

GSA

4.7 ohm

High current gate-drive. Wider PC-board trace to

limit inductance.

Secondary LSR2000 BPS

GSA

1 mF / 35 V SMD right

at pin. Usually also

47 mF further from pin

Secondary LSR2000 5VS

GSB

10 mF / 10 V SMD

right at pin

Note: this pin also has high internal current spikes,

hence larger capacitor right at the pin.

Secondary LSR2000

GSB

RIS resistor + 470 pF

/ 200 V capacitor

Note: the RIS resistor is typically split into two series

resistors to share the voltage rating. Series resistors

are placed as close as possible to the IS pin to limit

external noise coupling.

Secondary LSR2000 CMP

GSB

Initial values (150k +

2.2 nF) // 100 pF. All

components at pin

Compensation components may require modification

to optimize phase-gain response.

Secondary LSR2000

GSB

10 k lower resistor

value, at pin

The resistor divider 10 kW low-side resistor is used

to give a good balance between no-load consump-

tion and noise rejection. Lower values will give more

noise immunity but will also increase no-load

consumption.

Secondary LSR2000

GSB

RPS at pin

See data table for selection values.

Table 7.

Data Sheet Body Table.

Basic Layout Guidelines

The HiperLCS-2 is a high-frequency power device and requires careful

attention to circuit board layout in order to achieve maximum

performance. The bypass capacitors need to be positioned and laid

out carefully to minimize trace lengths to the pins they serve.

Surface mount (SMD) components are recommended for minimum

component and PC-board stray inductance.

The HiperLCS-2 has several sensitive pins, used for sensing analog

signals. Good device performance can be achieved by paying special

attention to the layout at and around these pins.

On the primary-side control, both the FL pin and L pin have may be

sensitive to layout.

The FL pin output is essentially a digital output, so for this pin the

issue is to ensure that the GP, FL and 5VL are all directly connected

between the primary and isolation devices. If the grounding is not

done correctly this can lead to potential noise pickup.

For the L pin this is a sensitive analog input pin. The L pin senses

input voltage via a resistor (typically 4 MW). The resistor is typically

made of a series of SMD resistors. Splitting the resistance into

several devices will minimize the voltage stress on each resistor.

There are two different examples of how to connect the L pin to VIN.

The first (incorrect) would be to place all the resistors close to VIN

and then run a long PC-board trace to the L pin. This is incorrect

since the node from resistor to L pin is high-impedance and a long

PC-board trace would allow noise pickup injected into the L pin. The

second (correct) method would be to place ALL the resistors close to

the L pin and run a long PC-board trace to VIN. This method is

correct since the node from resistor to VIN is very low-impedance

and thus very unlikely to pick-up noise. On the secondary-side

control, the FB, CMP, IS and D1/D2 pins may be sensitive to layout.

The FB pin is a high impedance voltage input pin. It is connected to

OUT via a resistor divider (RUPPER, RLOWER). VOUT is a low-impedence

node, so this may be the long PC-board connection. The node from

UPPER to RLOWER, is high impedance and should be placed as close and

tightly coupled as possible to the FB and GSB pins. The general

recommendation for R

LOWER is 10 kW, which is a good compromise

between no-load consumption and noise immunity. Further reducing

LOWER would increase noise immunity but increase no-load consumption.

Note that any noise injected into the FB pin could be observed as

duty-cycle and/or frequency variation.

The CMP pin is a high impedance current output and voltage-input

pin. The compensation network of one-resistor and two capacitors’ is

should be place as closely and tightly coupled as possible to the CMP

LCS7260C Datasheet(PDF) 13 Page - Power Integrations, Inc.

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