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DS20005054D-page 21

SST25VF020B

TABLE 6-5:

RELIABILITY CHARACTERISTICS

Symbol

Parameter

Minimum Specification

Unit

Test Method

NEND(1)

Endurance

100,000

Cycles

JEDEC Standard A117

TDR(1)

Data Retention

100

Years

JEDEC Standard A103

ILTH(1)

Latch Up

100 + IDD

mA

JEDEC Standard 78

Note 1: This parameter is measured only for initial qualification and after a design or process change that could

affect this parameter.

TABLE 6-6:

AC OPERATING CHARACTERISTICS

Symbol

Parameter

33 MHz

80 MHz

Units

Min.

Max.

Min.

Max.

FCLK

Serial Clock Frequency(1)

—

33

—

80

MHz

TSCKH

Serial Clock High Time

13

—

6

—

ns

TSCKL

Serial Clock Low Time

13

—

6

—

ns

TSCKR

Serial Clock Rise Time (slew rate)(2)

0.1

—

0.1

—

V/ns

TSCKF

Serial Clock Fall Time (slew rate)

0.1

—

0.1

—

V/ns

TCES

CE# Active Setup Time(3)

5

—

5

—

ns

TCEH

CE# Active Hold Time(3)

5

—

5

—

ns

TCHS

CE# Not Active Setup Time(3)

5

—

5

—

ns

TCHH

CE# Not Active Hold Time(3)

5

—

5

—

ns

TCPH

CE# High Time

50

—

50

—

ns

TCHZ

CE# High-to-High Z Output

—

15

—

7

ns

TCLZ

SCK Low-to-Low Z Output

0

—

0

—

ns

TDS

Data In Setup Time

2

—

2

—

ns

TDH

Data In Hold Time

4

—

4

—

ns

THLS

HOLD# Low Setup Time

5

—

5

—

ns

THHS

HOLD# High Setup Time

5

—

5

—

ns

THLH

HOLD# Low Hold Time

5

—

5

—

ns

THHH

HOLD# High Hold Time

5

—

5

—

ns

THZ

HOLD# Low-to-High Z Output

—

7

—

7

ns

TLZ

HOLD# High-to-Low Z Output

—

7

—

7

ns

TOH

Output Hold from SCK Change

0

—

0

—

ns

TV

Output Valid from SCK

—

10

—

6

ns

TSE

Sector Erase

—

25

—

25

ms

TBE

Block Erase

—

25

—

25

ms

TSCE

Chip Erase

—

50

—

50

ms

TBP

Byte Program

—

10

—

10

µs

Note 1: Maximum clock frequency for Read instruction, 03H, is 33 MHz.

2: Maximum Rise and Fall time may be limited by TSCKH and TSCKL requirements.

3: Relative to SCK.