SST26WF064C datasheet(13/94 Pages) MICROCHIP

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 2016-2018 Microchip Technology Inc.

DS20005430C-page 13

SST26WF064C

4.7

Configuration Register

The Configuration register is a Read/Write register that

stores a variety of configuration information. See Table

4-4 for the function of each bit in the register.

4.7.1

I/O CONFIGURATION (IOC)

The I/O Configuration (IOC) bit re-configures the I/O

pins. The IOC bit is set by writing a ‘1’ to Bit 1 of the

Configuration register. When IOC bit is ‘0’ the WP# pin

and HOLD# pin are enabled (SPI or Dual Configuration

setup). When IOC bit is set to ‘1’ the SIO2 pin and SIO3

pin are enabled (SPI Quad I/O Configuration setup).

The IOC bit must be set to ‘1’ before issuing the follow-

ing SPI commands: SQOR (6BH), SQIOR (EBH),

RBSPI (ECH), SPI Quad page program (32H), SQOR-

DTR (6DH), and SQIOR-DTR (EDH). Without setting

the IOC bit to ‘1’, those SPI commands are not valid.

The I/O configuration bit does not apply when in SQI

mode. The default at power-up for the SST26WF064C

is ‘0’.

4.7.2

BLOCK-PROTECTION VOLATILITY

STATE (BPNV)

The Block-Protection Volatility State bit indicates

whether any block has been permanently locked with

the non-Volatile Write-Lock Lock-Down register

(nVWLDR). When no bits in the nVWLDR have been

set (the default state from the factory) the BPNV bit is

`1'; when one or more bits in the nVWLDR are set to `1'

the BPNV bit will also be `0' from that point forward,

even after power-up.

4.7.3

RESET/HOLD ENABLE (RSTHLD)

The Reset/Hold Enable (RSTHLD) bit is a non-volatile

bit that configures RESET#/HOLD#/SIO3 pin to be

either Reset# pin or Hold# pin.

4.7.4

WRITE-PROTECT ENABLE (WPEN)

The Write-Protect Enable (WPEN) bit is a non-volatile

bit that enables the WP# pin.

The Write-Protect (WP#) pin and the Write-Protect

Enable (WPEN) bit control the programmable hard-

ware write-protect feature. Setting the WP# pin to low,

and the WPEN bit to ‘1’, enables Hardware write-pro-

tection. To disable Hardware write protection, set either

the WP# pin to high or the WPEN bit to ‘0’. There is

latency associated with writing to the WPEN bit. Poll

the BUSY bit in the Status register, or wait TWPEN, for

the completion of the internal, self-timed Write opera-

tion. When the chip is hardware write protected, only

Write operations to Block-Protection and Configuration

registers are disabled.See “Hardware Write Protection”

on page 8 and Table 4-1 for more information about the

functionality of the WPEN bit.

TABLE 4-4:

CONFIGURATION REGISTER

Bit

Name

Function

Default at Power-up

Read/Write (R/W)

0RES

Reserved

IOC

I/O Configuration

1 = WP# and RESET# or HOLD# pins disabled

0 = WP# and RESET# or HOLD# pins enabled

1. SST26WF064C default at Power-up is ‘0’

R/W

2RES

Reserved

BPNV

Block-Protection Volatility State

1 = No memory block has been permanently locked

0 = Any block has been permanently locked

4RES

Reserved

5RES

Reserved

RSTHLD

RESET# pin or HOLD# pin Enable

1 = RESET# pin enabled

0 = HOLD# pin enabled

2. Factory default setting. This is a non-volatile bit; default at power-up will be the setting prior to power-down.

R/W

WPEN

Write-Protection Pin (WP#) Enable

1 = WP# enabled

0 = WP# disabled

R/W

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