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ATF1504ASV Datasheet(PDF) 10 Page - Microchip Technology |
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ATF1504ASV Datasheet(HTML) 10 Page - Microchip Technology |
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10 / 30 page  2019 Microchip Technology Inc. DS20006185A-page 10 ATF1504ASV/ATF1504ASVL tACL Array Clock Low Time 6 — 8 — ns tCNT Minimum Clock Global Period — 13 — 17 ns fCNT Maximum Internal Global Clock Frequency 76.9 — 66 — MHz tACNT Minimum Array Clock Period — 13 — 17 ns fACNT Maximum Internal Array Clock Frequency 76.9 — 58.8 — MHz fMAX Maximum Clock Frequency 100 — 83.3 — MHz tIN Input Pad and Buffer Delay — 2 — 2.5 ns tIO I/O Input Pad and Buffer Delay — 2 — 2.5 ns tFIN Fast Input Delay — 2 — 2 ns tSEXP Foldback Term Delay — 8 — 10 ns tPEXP Cascade Logic Delay — 1 — 1 ns tLAD Logic Array Delay — 6 — 8 ns tLAC Logic Control Delay — 3.5 — 4.5 ns tIOE Internal Output Enable Delay — 3 — 3 ns tOD1 Output Buffer and Pad Delay (Slow slew rate = OFF; VCCIO = 3.3V; CL =35pF) —3 —4 ns tOD3 Output Buffer and Pad Delay (Slow slew rate = ON; VCCIO = 3.3V; CL =35pF) —5 —6 ns tZX1 Output Buffer Enable Delay (Slow slew rate = OFF; VCCIO = 3.3V; CL =35pF) —7 —9 ns tZX3 Output Buffer Enable Delay (Slow slew rate = ON; VCCIO = 3.3V; CL =35pF) —10— 11 ns tXZ Output Buffer Disable Delay (CL =5pF) — 6 — 7 ns tSU Register Setup Time 5 — 6 — ns tH Register Hold Time 4 — 5 — ns tFSU Register Setup Time of Fast Input 2 — 2 — ns tFH Register Hold Time of Fast Input 2 — 2 — ns tRD Register Delay — 2 — 2.5 ns tCOMB Combinatorial Delay — 2 — 3 ns tIC Array Clock Delay — 6 — 7 ns tEN Register Enable Time — 6 — 7 ns tGLOB Global Control Delay — 2 — 3 ns tPRE Register Preset Time — 4 — 5 ns tCLR Register Clear Time — 4 — 5 ns tUIM Switch Matrix Delay — 2 — 2.5 ns TABLE 1-4: AC CHARACTERISTICS (CONTINUED) Symbol Parameter -15 -20 Units Min. Max. Min. Max. |
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