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S32K311NHT0MPAST Datasheet(PDF) 10 Page - NXP Semiconductors |
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S32K311NHT0MPAST Datasheet(HTML) 10 Page - NXP Semiconductors |
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10 / 141 page  Xbar (64 bit) Fabric 8 MB Pflash with ECC Memory External Memory IF 1 x Ethernet, 1 Gbps AVB/TSN 6 x FlexCAN all ch support CAN FD 16 x LPUART (LIN) Network 32 ch FlexIO Emulating UART, I2C, SPI I2S, SENT, PWM Communication 128 kB Dflash with ECC 1152 kB RAM with ECC Include 192 kB TCM FXOSC (8-40 MHz) Memory OTA ready - RWW, A/B swap External Flash/Ram expansion by QuadSPI • • CPU Platform Two independent Arm M7 cores Optimized for Real- time with zero wait I/D-TCM • • Motor Control On-chip motor control subsystem Offloading CPU • • Future Proof Security/OTA ISO26262 Compliant Safety System Scalable Arm platform Optimized for LOW power Rich Network/Communication Interface • • • • • Safety HW redundancy MBIST/LBIST/Self Test Clock/Voltage monitor Centralized error detection ASIL B compliant • • • • • Security HW accl for AES 256, RSA 4096, ECC 521 Firmware included, upgradable Side-channel physical protection Meet Evita Full function goal • • • • Network/ Communication Ethernet (TSN), CAN/ CAN FD, LIN SAI for Audio Flexible IO emulation • • • System FIRC (48 MHz) CPU Platform Cortex-M7 240 MHz FPU, DSP I-cache D-cache SIRC (32 kHz) SXOSC (32 kHz) 2 x PLL 32ch DMAMUX 32ch ext. INT/WKUP 6 x LPSPI 2 x LPI2C 2 x SAI (TDM, I2S) Analog/Timers BCTU (Body Control Trigger Unit) 3 x 24 ch 12 bit ADC LCU (Logic Control Unit) 3 x 24 ch 16 bit eMIOS Timer 3 x LPCMP Functional Safety CMU FCCU MPU SWT EIM/ERM STCU2 CRC Security: HSE-B Cortex-M0+ RAM XRDC Access control Lifecycle Management Asymmetric Hardware Accelerators Symmetric Hardware Accelerators TRNG/PRNG Debug/Trace (SWD/JTAG/ETB) Cortex-M7 240 MHz FPU, DSP I-cache D-cache 1 x QuadSPI Up to 2 Gbps 8 bit data width 1 x uSDHC 32 bit RTC Figure 10. S32K328: ASIL B Dual Core 8MB General Purpose MCU Xbar (64 bit) Fabric 8 MB Pflash with ECC Memory External Memory IF 1 x Ethernet, 1 Gbps AVB/TSN 8 x FlexCAN all ch support CAN FD 16 x LPUART (LIN) Network 32 ch FlexIO Emulating UART, I2C, SPI I2S, SENT, PWM Communication 128 kB Dflash with ECC 1152 kB RAM with ECC Include 384 kB TCM FXOSC (8-40 MHz) Memory OTA ready - RWW, A/B swap External Flash/Ram expansion by QuadSPI • • CPU Platform Three independent Arm M7 cores Optimized for Real- time with zero wait I/D-TCM • • Motor Control On-chip motor control subsystem Offloading CPU • • Future Proof Security/OTA ISO26262 Compliant Safety System Scalable Arm platform Optimized for LOW power Rich Network/Communication Interface • • • • • Safety HW redundancy MBIST/LBIST/Self Test Clock/Voltage monitor Centralized error detection ASIL D compliant • • • • • Security HW accl for AES 256, RSA 4096, ECC 521 Firmware included, upgradable Side-channel physical protection Meet Evita Full function goal • • • • Network/ Communication Ethernet (TSN), CAN/ CAN FD, LIN SAI for Audio Flexible IO emulation • • • System FIRC (48 MHz) CPU Platform SIRC (32 kHz) SXOSC (32 kHz) 2 x PLL 32ch DMA and DMAMUX 32ch ext. INT/WKUP 6 x LPSPI 2 x LPI2C 2 x SAI (TDM, I2S) Analog/Timers BCTU (Body Control Trigger Unit) 3 x 24 ch 12 bit ADC LCU (Logic Control Unitl 3 x 24 ch 16 bit eMIOS Timer 3 x LPCMP Functional Safety CMU FCCU MPU SWT EIM/ERM STCU2 CRC Security: HSE-B Cortex-M0+ RAM XRDC Access control Lifecycle Management Asymmetric Hardware Accelerators Symmetric Hardware Accelerators TRNG/PRNG Debug/Trace (SWD/JTAG/ETB) Cortex-M7 240 MHz FPU, DSP I-cache D-cache Cortex-M7 240 MHz FPU, DSP I-cache D-cache Cortex-M7 240 MHz FPU, DSP I-cache D-cache 1 x QuadSPI Up to 2 Gbps 8 bit data width 1 x uSDHC 32 bit RTC Figure 11. S32K338: ASIL B Three Core 8MB General Purpose MCU NXP Semiconductors Block diagram S32K3xx Data Sheet, Rev. 6, 11/2022 Data Sheet: Technical Data Preliminary Information 10 / 141 |
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