Philips Semiconductors

Product specification

74F154

Decoder/demultiplexer

2

1990 Jan 08

853–1155 98493

FEATURES

DESCRIPTION

The 74F154 decoder accepts four active High binary address inputs

and provides 16 mutually exclusive active Low outputs. The 2-input

Enable (E0, E1) gate can be used to strobe the decoder to eliminate

the normal decoding “glitches” on the outputs, or it can be used for

expansion of the decoder. The enable gate has two AND’ed inputs

which must be Low to enable the outputs.

The 74F154 can be used as 1-of-16 demultiplexer by using one of

the Enable inputs as the multiplexed data input. When the other

Enable is Low, the addressed output will follow the state of the

applied data.

TYPE

TYPICAL

PROPAGATION

DELAY

TYPICAL

SUPPLY CURRENT

(TOTAL)

74F154

5.5 ns

26mA

ORDERING INFORMATION

DESCRIPTION

COMMERCIAL RANGE

PKG DWG #

24-pin plastic Slim

DIP (300mil)

N74F154N

SOT222-1

24-pin plastic SOL

N74F154D

SOT137-1

PIN CONFIGURATION

SF00681

Q0

Q1

Q2

Q3

Q4

Q5

Q6

Q7

Q8

Q9

Q10

A0

A1

A2

A3

E0

E1

Q14

Q15

Q13

Q12

Q11

GND

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

INPUT AND OUTPUT LOADING AND FAN-OUT TABLE

PINS

DESCRIPTION

74F (U.L.) HIGH/LOW

LOAD VALUE HIGH/LOW

A0 – A3

Data inputs

1.0/1.0

20

µA/0.6mA

E0, E1

Enable inputs

1.0/1.0

20

µA/0.6mA

Q0 – Q15

Data outputs

50/33

1.0mA/20mA

NOTE: One (1.0) FAST unit load is defined as: 20

µA in the High state and 0.6mA in the Low state.

LOGIC SYMBOL

SF00680

4

5

6

A0

A3

1

2

7

8

9

3

13

14

10

15

16

17

11

18

19

21

20

23

22

Q0

Q1

Q2

Q3

Q4

Q5

Q6

Q7

Q8

Q9

Q10

Q12

Q13

Q14

Q15

Q11

A1

A2

GND=Pin 12

E1

E0

LOGIC SYMBOL (IEEE/IEC)

SF00682

4

5

6

0

3

1

2

7

8

9

3

13

14

10

15

16

17

11

18

19

21

20

23

22

DX

G

0

16