MIC33M656 datasheet(21/46 Pages) MICROCHIP

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 2019 Microchip Technology Inc.

DS20006256A-page 21

MIC33M656

4.12

Undervoltage Protection (UVLO)

Undervoltage protection ensures that the IC has

enough voltage to bias the internal circuitry properly

and provide sufficient gate drive for the power

MOSFETs. When the input voltage starts to rise, both

power MOSFETs are off and the Power Good output is

pulled low. The IC starts at approximately 2.225V typi-

cal and has a nominal 153 mV of hysteresis to prevent

chattering between the UVLO high and low states.

4.13

Overtemperature Fault

The MIC33M656 monitors the die junction temperature

to keep the IC operating properly. If the IC junction

temperature exceeds +118°C, the warning flag,

“OT_WARN”, is set, but does not affect the operation

mode. It automatically resets if the junction temperature

drops below the temperature threshold. If the IC junction

temperature exceeds +165°C, both power MOSFETs

are immediately turned off. The IC is allowed to start

when the die temperature falls below +143°C.

During the Fault condition, several changes will occur in

the STATUS Register. The OT bit will go high, indicating

the junction temperature reached +165°C, while the

OT_WARN automatically resets. If the controller is

enabled to restart after the first thermal shutdown event

(OT_LATCH bit in CTRL2 register is set), the SSD bit will

go low and the HICCUP bit will go high. Finally, the PG bit

in the FAULT register (address 0x03) will go low and the

PG pin will be pulled low until the output voltage has

restarted and is once again in regulation. The I2C inter-

face remains active and all the values stored in registers

are maintained. When the die temperature decreases

below the lower thermal shutdown threshold, and the

MIC33M656 resumes switching with the output voltage

going back in regulation, the global Power Good output is

pulled high, but the Overtemperature Fault bit, OT, is still

set to ‘1’. To clear the Fault, either recycle input power or

write a logic ‘0’ to the Overtemperature bit, OT, in the

FAULT register.

During recovery from a thermal shutdown event, if the

regulator hits another thermal shutdown event before

Power Good can be achieved, the controller will again

reset. If this happens four times in a row, the part will be in

a Latch-Off state and the MOSFETs are permanently

latched off. The LATCH_OFF bit in the STATUS Register

will be set to ‘1’, which will latch off the MIC33M656. The

device can be restarted by toggling the enable input, by

recycling the input power or by software Enable Control

(EN_CON). This latch-off feature eliminates the thermal

stress on the MIC33M656 during a Fault event. The

OT_LATCH bit in the CTRL2 register can be set to ‘0’,

which will cause this latch-off to happen after the first over-

temperature event, instead of waiting for four consecutive

overtemperatures. This is a more conservative approach

to protect the part and is available to the user.

4.14

Safe Start-up into a Pre-Biased

Output

The MIC33M656 is designed for safe start-up into a

pre-biased output in forced PWM. This feature prevents

high negative inductor current flow in a pre-bias condition,

which can damage the IC. This is achieved by not allow-

ing forced PWM until the control loop commands eight

switching cycles. After eight cycles, the low-side negative

current limit is switched from 0A to -3A. The cycle counter

is reset to zero if the Enable pin is pulled low, or an input

undervoltage condition or any other Fault is detected.

4.15

Current Limiting

The MIC33M656 regulator uses both high-side and

low-side current sense for current limiting. When the

high-side current sense threshold is reached, the

high-side MOSFET is turned off and the low-side

MOSFET is turned on. The low-side MOSFET stays on

until the current falls to 80% of the high-side current

threshold value, then the high-side current can be turned

on again. If the overload condition lasts for more than

seven cycles, the MIC33M656 enters hiccup current lim-

iting and both MOSFETs are turned off. There is a 1 ms

cool-off period before the MOSFETs are allowed to be

turned on. If the regulator has another hiccup event

before it reaches the Power Good threshold on restart, it

will again turn off both MOSFETs and wait for 1 ms. If

this happens more than three times in a row, then the

part will enter the Latch-Off state, which will permanently

turn off both MOSFETs until the part is reset by toggling

the EN pin, recycling power or via an I2C command.

During a hiccup event, the HICCUP bit in the STATUS

output has recovered. The Power Good FAULT register

bit, PG, will also go low and the PG pin will be pulled low.

In latch-off, the LATCH_OFF status bit is set to ‘1’.

The high-side current limit can be programmed by

setting the ILIM[1:0] bits in the CTRL1 register. For max-

imum efficiency and current limit precision, the highest

current limit must be programmed together with a higher

TON setting (corresponding to a lower frequency).

4.16

Thermal Considerations

Although the MIC33M656 is capable of delivering up to

6A under load, the package thermal resistance and the

device internal power dissipation may dictate some

limitations to the continuous output current.

As a reference, for VIN = 5V, VOUT = 1V, IOUT = 5A, the

DT100108 Evaluation Board application shows a

stable +40°C chip self-heating.

For VIN = 5V, VOUT = 3.3V, the same self-heating is

produced at about 4A.

If operated above the rated junction temperature,

electrical parameters may drift beyond characterized

specifications. The MIC33M656 is protected under all

circumstances by thermal shutdown.

MIC33M656 Datasheet(PDF) 21 Page - Microchip Technology

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