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UPSD3422EB40U6 Datasheet(PDF) 223 Page - STMicroelectronics |
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UPSD3422EB40U6 Datasheet(HTML) 223 Page - STMicroelectronics |
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223 / 300 page  Obsolete Product(s) - Obsolete Product(s) Obsolete Product(s) - Obsolete Product(s) UPSD3422, UPSD3433, UPSD3434, UPSD3454 PSD module 223/300 Figure 74. DPLD logic array 28.5.28 General PLD (GPLD) The GPLD is used to create general system logic. Figure 73 on page 221 shows the architecture of the entire GPLD, and Figure 75 on page 224 shows the relationship between one OMC, one IMC, and one I/O port pin, which is representative of pins on Ports A, B, and C. It is important to understand how these elements work together. A more detailed description will follow for the three major blocks (OMC, IMC, I/O Port) shown in Figure 75. Figure 75 also shows which csiop registers to access for various PLD and I/O functions. The GPLD contains: ● 16 Output Macrocells (OMC) ● 20 Input Macrocells (IMC) ● OMC Allocator ● Product Term Allocator inside each OMC ● AND-OR Array capable of generating up to 137 product terms ● Three I/O Ports, A, B, and C FS0 FS1 FS7 FS6 FS5 FS4 FS3 FS2 Main Flash memory sector Selects CSBOOT0 CSBOOT3 CSBOOT2 CSBOOT1 Secondary Flash memory sector Selects RS0 SRAM Select CSIOP I/O & control registers Select ECS0 ECS1 External Chip- Selects (Port D) PSEL0 PSEL1 Peripheral I/O mode range Selects 8032 address (A0 - A15) 16 4 1 Power-down indicator (PDN) 1 Pin input ports A, B, C (IMCs) 20 Pin input port D 2 OMC feedback (MCELLAB.FB0-7) 8 Page register (PGR0 - PGR7) 8 8 1 OMC feedback (MCELLBC.FB0-7) PLD input bus 3 3 3 3 3 3 3 3 3 3 3 3 2 1 1 1 1 1 Number of product terms AI06601b PSM module reset (RST) Flash memory prog status (RDYBSY) 8032 CNTL (RD, WR, PSEN, ALE) Obsolete Product(s) - Obsolete Product(s) |
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