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UPSD3422EB40U6 Datasheet(PDF) 241 Page - STMicroelectronics |
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UPSD3422EB40U6 Datasheet(HTML) 241 Page - STMicroelectronics |
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241 / 300 page ![]() Obsolete Product(s) - Obsolete Product(s) Obsolete Product(s) - Obsolete Product(s) UPSD3422, UPSD3433, UPSD3434, UPSD3454 PSD module 241/300 mode, making the pin suitable for input mode (read by the input buffer shown in Figure 79 on page 232). Figure 79 shows the three sources that can control the pin output enable signal: a product term from AND-OR array; the csiop Direction register; or the Peripheral I/O Mode logic (Port A only). The csiop Enable Out registers represent the state of the final output enable signal for each port pin driver, and are defined in Table 196 on page 242 through Table 199 on page 242. Table 192. Port A pin drive select register(1) (2) (3)(address = csiop + offset 08h) 1. Port A not available on 52-pin UPSD34xx devices. 2. For each bit, 1 = pin drive type is selected, 0 = pin drive type is default mode, CMOS push/pull. 3. Default state for register is 00h after reset or power-up. Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 PA7 open drain PA6 open drain PA5 open drain PA4 open drain PA3 slew rate PA2 slew rate PA1 slew rate PA0 slew rate Obsolete Product(s) - Obsolete Product(s) |
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