UPSD3422EB40U6 datasheet(244/300 Pages) STMICROELECTRONICS

244 / 300 page

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PSD module

UPSD3422, UPSD3433, UPSD3434, UPSD3454

244/300

28.5.49

Port B structure

Port B supports the following operating modes:

●

MCU I/O Mode

●

GPLD Output Mode from Output Macrocells MCELLABx, or MCELLBCx (OMC

allocator routes these signals)

●

GPLD Input Mode to Input Macrocells IMCBx

●

Latched Address Output Mode

Port B also supports Open Drain/Slew Rate output drive type options using the csiop Drive

Select registers. Pins PB0-PB3 can be configured to fast slew rate, pins PB4-PB7 can be

configured to Open Drain Mode.

See Figure 85 for detail.

Figure 85.

Port B structure

Note:

Port pins PB0-PB3 are capable of Fast Slew Rate output drive option. Port pins PB4-PB7

are capable of Open Drain output option.

I/O port B

logic

Direction

Drive Select

Control

Data out

(MCUI/O)

Enable Out

Data in (MCUI/O)

PT Output Enable (.OE)

Latched addr bit

Output

Enable

Output

Enable

Typical

pin, port B

PSD module reset

One of 6

CSIOP

registers

Output

Select

From OMC output

(MCELLABx or MCELLBCx)

From PLD

input bus

From AND-

OR array

From OMC

allocator

CLR

Direction

Drive

Control

(MCUI/O)

data out

8032

Reset

PSDsoft

8032 RD

To IMCs

CSIOP

registers

Drive type select

(1)

8032

data

bits

8032

DATA

BIT

Pin input

CMOS

buffer

hysteresis

VDD

output

1 = Open

drain,

PB4 - PB7

1 = Fast

Slew rate,

PB0 - PB3

IMCB0 - IMCB7

AI09180

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Product(s)

UPSD3422EB40U6 Datasheet(PDF) 244 Page - STMicroelectronics

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