UPSD3422EB40U6 datasheet(247/300 Pages) STMICROELECTRONICS

247 / 300 page

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PSD module

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Port D pins can also be configured in PSDsoft as pins for other dedicated functions:

●

PD1 can be used as a common clock input to all 16 OMC Flip-flops (see

Section 28.1.11: OMCs on page 195) and also the Section 28.5.53: Automatic power-

down (APD) on page 250.

●

PD2 can be used as a common chip select signal (CSI) for the Flash and SRAM

memories on the PSD module (see Section 28.5.55: Chip select input (CSI) on

page 253). If driven to logic ’1’ by an external source, CSI will force the Flash memory

into standby mode regardless of what other internal memory select signals are doing

on the PSD module. This is specified in PSDsoft as “PSD Chip Select Input, CSI”.

Port D also supports the Fast Slew Rate output drive type option using the csiop Drive

Select registers.

Figure 87.

Port D structure

Note:

Optional function on a specific Port D pin.

I/O port D

logic

Direction

Drive select

Data out

(MCUI/O)

Enable Out

Data in (MCUI/O)

PT Output Enable (.OE)

Output

Enable

Typical

pin, port D

PSD module reset

One of 5

CSIOP

Registers

From DPLD external chip (ECSx)

From PLD

input bus

From AND-

OR array

From DPLD

CLR

Directions

Drive

(MCUI/O)

Data out

8032

Reset

PSDsoft

8032 RD

To power management and PLD input bus

CSIOP

registers

Drive select type

8032

data

bits

8032

DATA

BIT

Pin input

CMOS

buffer

hysteresis

VDD

output

1 = Fast

Slew rate

PD1. PIN, PD2.PIN

Directly to PLD input bus, no IMC

CSI

(1)

To power management

CLKIN

(1)

AI09182

Output

Enable

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UPSD3422EB40U6 Datasheet(PDF) 247 Page - STMicroelectronics

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