UPSD3422EB40U6 datasheet(250/300 Pages) STMICROELECTRONICS

250 / 300 page

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PSD module

UPSD3422, UPSD3433, UPSD3434, UPSD3454

250/300

28.5.53

Automatic power-down (APD)

The APD unit shown in Figure 73 on page 221 puts the PSD module into power-down mode

by monitoring the activity of the 8032 Address Latch Enable (ALE) signal. If the APD unit is

enabled by writing a logic ’1’ to Bit 1 of the csiop PMMR0 register, and if ALE signal activity

has stopped (8032 in sleep mode), then the four-bit APD counter starts counting up. If the

ALE signal remains inactive for 15 clock periods of the CLKIN signal (pin PD1), then the

APD counter will reach maximum count and the power down indicator signal (PDN) goes to

logic ’1’ forcing the PSD module into power-down mode. During this time, all buffers on the

PSD module for 8032 address and data signals are disabled in silicon, preventing the PSD

module Flash memories from waking up from standby mode, even if noise or other devices

Bit 3

Blocking Bit,

RD to

PLDs(2)

0 =

8032 RD input to the PLD Input Bus is not blocked.

1 =

off

8032 RD input to PLD Input Bus is blocked, saving power.

Bit 4

Blocking Bit,

PSEN to

PLDs(2)

0 =

8032 PSEN input to the PLD Input Bus is not blocked.

1 =

off

8032 PSEN input to PLD Input Bus is blocked, saving power.

Bit 5

Blocking Bit,

ALE to

PLDs(2)

0 =

8032 ALE input to the PLD Input Bus is not blocked.

1 =

off

8032 ALE input to PLD Input Bus is blocked, saving power.

Bit 5

Blocking Bit,

PC7 to

PLDs(2)

0 =

Pin PC7 input to the PLD Input Bus is not blocked.

1 =

off

Pin PC7 input to PLD Input Bus is blocked, saving power.

Bit 7

Not used, and should be set to zero.

All the bits of this register are cleared to zero following power-up. Subsequent Reset (RST) pulses do not

clear the registers.

Blocking bits should be set to logic ’1’ only if the signal is not needed in a DPLD or GPLD logic equation.

Table 202.

Power management mode register PMMR3 (address = csiop + offset

C7h)(1)

All the bits of this register are cleared to zero following power-up. Subsequent Reset (RST) pulses do not

clear the registers.

Bit 0

Not used, and should be set to zero.

Bit 1

FORCE_PD

0 =

off

APD counter will cause Power-Down Mode if APD is enabled.

1 =

Power-Down mode will be entered immediately regardless of APD

activity.

Bit 3-

Not used, and should be set to zero.

Table 201.

Power management mode register PMMR2 (address = csiop + offset

B4h)(1) (continued)

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UPSD3422EB40U6 Datasheet(PDF) 250 Page - STMicroelectronics

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