EM6821 datasheet(22/68 Pages) EMMICRO

22 / 68 page

EM6821

www.emmicroelectronic.com

For POWER SAVING one can switch off the port SP pull resistors between two read phases. No cross current

flows in the input amplifier while the port SP is not read.

This power saving feature must only be used in tristate mode (OM[0,1]=0). The recommended order is :

• switch on the pull resistor.

• allow sufficient time - RC constant - for the pull resistor to drive the line to either VSS or VDD.

• Read the port SP

• Switch off the pull resistor

Minimum time with current on the pull resistor is 4 periods of the system clock, if the RC constant is lower than

1 system clock period. Adding a NOP before reading moves the number of periods with current in the pull

resistor to 6 and the maximum RC delay to 3 clock periods.

6.6.3 Nch. Open Drain Outputs

The port SP outputs can be configured as either CMOS or Nch. open drain outputs.

In CMOS both logic ‘1’ and ‘0’ are driven out on the terminal.

In Nch. open drain only the logic ‘0’ is driven out on the terminal, the logic ‘1’ value is high impedance or

defined by the internal pull-up resistor (if existing).

6.6.4 General Functional Description

After power on or after any reset the serial interface is in serial slave mode with Start and Status set to 0, LSB

first, negative shift edge and all outputs are in high impedance state.

When the Start bit is set, the shift operation is enabled and the serial interface is ready to transmit or receive

data, eight shift operations are performed: 8 serial data values are read from the data input terminal into the

shift register and the previous loaded 8-bits are send out via the data output terminal. After the eight shift

operation, an interrupt is generated, and the Start bit is reset.

Parallel to serial conversion procedure ( master mode example ).

Write to RegSCntl1 serial control (clock freq. in master mode, edge and MSB/LSB select).

Write to RegSDataL and RegSDataH (shift out data values).

Write to RegSCntl2 (Start=1, mode select, status).

---> Starts the shift out

After the eighth clock an interrupt is generated, Start becomes low. Then, interrupt handling

Serial to parallel conversion procedure (slave mode example).

Write to RegSCntl1 (slave mode, edge and MSB/LSB select).

Write to RegSCntl2 (Start=1, mode select, status).

After eight serial clocks an interrupt is generated, Start becomes low.

Interrupt handling.

Shift register RegSDataL and RegSDataH read.

A new shift operation can be authorized.

Figure 15. CMOS or Nch. Open Drain outputs

I / O

T erm inal

SP[n]

MUX

Active Pull-up

for High State

DR[n]

Serial Interface

Output

T ristate O utput

Buffer : High

Im pedance for

Data = 1

Data

I / O

Term inal

SP[n]

MUX

DR[n]

Serial Interface

Output

Tristate O utput

Buffer : closed

Data

CM O S O utput

Nch. O pen Drain O utput

EM6821 Datasheet(PDF) 22 Page - EM Microelectronic - MARIN SA

EM6821 Datasheet(HTML) 22 Page - EM Microelectronic - MARIN SA

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68

Datasheet Download

Link URL