ATMEGA325SLASHV datasheet(97/347 Pages) ATMEL

97 / 347 page

ATmega325/3250/645/6450

2570A–AVR–09/04

Figure 40. 16-bit Timer/Counter Block Diagram

(1)

Note:

1. Refer to Figure 1 on page 2, “Alternate Functions of Port D” on page 62, and “Alter-

nate Functions of Port G” on page 67for Timer/Counter1 pin placement and

description.

Registers

The Timer/Counter (TCNT1), Output Compare Registers (OCR1A/B), and Input Capture

accessing the 16-bit registers. These procedures are described in the section “Access-

ing 16-bit Registers” on page 99. The Timer/Counter Control Registers (TCCR1A/B) are

8-bit registers and have no CPU access restrictions. Interrupt requests (abbreviated to

Int.Req. in the figure) signals are all visible in the Timer Interrupt Flag Register (TIFR1).

All interrupts are individually masked with the Timer Interrupt Mask Register (TIMSK1).

TIFR1 and TIMSK1 are not shown in the figure.

The Timer/Counter can be clocked internally, via the prescaler, or by an external clock

source on the T1 pin. The Clock Select logic block controls which clock source and edge

the Timer/Counter uses to increment (or decrement) its value. The Timer/Counter is

inactive when no clock source is selected. The output from the Clock Select logic is

referred to as the timer clock (clk

T1).

The double buffered Output Compare Registers (OCR1A/B) are compared with the

Timer/Counter value at all time. The result of the compare can be used by the Waveform

Generator to generate a PWM or variable frequency output on the Output Compare pin

(OC1A/B). See “Output Compare Units” on page 105.. The compare match event will

Clock Select

Timer/Counter

OCRnA

OCRnB

ICRn

TCNTn

Waveform

Generation

Waveform

Generation

OCnA

OCnB

Noise

Canceler

ICPn

Fixed

TOP

Values

Edge

Detector

Control Logic

= 0

TOP

BOTTOM

Count

Clear

Direction

TOVn

(Int.Req.)

OCnA

(Int.Req.)

OCnB

(Int.Req.)

ICFn (Int.Req.)

TCCRnA

TCCRnB

( From Analog

Comparator Ouput )

Edge

Detector

( From Prescaler )

clk

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