STE2004 datasheet(60/66 Pages) STMICROELECTRONICS

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STE2004

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Figure 75. Serial interface Timing

Notes: 1.

2. All timing values are valid within the operating supply voltage and ambient temperature ranges and referenced to VIL and VIH with

an input voltage swing of VSS to VDD

3. Cb is the capacitive load for each bus line.

4. For bus line loads Cb between 100 and 400pF the timing parameters must be linearly interpolated

5. CVLCD is the filtering CApacitor on VLCD

6. Trise and Tfall (30%-70%) -10ns

7. I2C bus AC Characteristics are tested by correlation

Table 23 Electrical Characteristics (continued)

AC OPERATION (continued)

(VDD1 = 1.7 to 3.6 V; VDD2 = 1.75 to 4.5 V; Vss1,2 = 0V; VLCD = 4.5 to 15 V; Tamb =-40 to 85°C; unless otherwise specified)

Symbol

Parameter

Test Condition

Min.

Typ.

Max.

Unit

SERIAL INTERFACE

FSCLK

Clock Frequency

VDD1 = 1.7V;

MHz

TCYC

Clock Cycle SCLK

125

TPWH1

SCLK pulse width HIGH

TPWL1

SCLK Pulse width LOW

TS2

CS setup time

VDD1 = 1.7V

TH2

CS hold time

TPWH2

CS minimum high time

TS3

SD/C setup time

TH3

SD/C hold time

TS4

SDIN setup time

TH4

SDIN hold time

TS5

SDOUT Access Time

TH5

SDOUT Disable Time vs. SCLK

TH6

SDOUT Disable Time vs. CS

D/C

tS2

tS3

tS4

tH2

tPWH2

SDIN

SCLK

tH3

tH4

tPWL1

tWH1

tS2

tCYC

SOUT

tS5

tH5

tH6

LR0096

frame

osc

960

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