STE2004DIE2 datasheet(35/66 Pages) STMICROELECTRONICS

Part #	STE2004DIE2

Description	102 X 65 SINGLE CHIP LCD CONTROLLER / DRIVER

PDF	66 Pages

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Manufacturer	STMICROELECTRONICS [STMicroelectronics]

Direct Link	http://www.st.com

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STE2004

Figure 47. 68000-series Parallel interface protocol in Reading Mode

Figure 48. 68000-series Parallel interface protocol in Reading Mode (Several Bytes)

4.3.4 8080-series parallel interface

If CS is low after the positive edge of RES, the 8080 parallel interface is ready to receive or transmit data.

While CS pin is high the 8080 Parallel interface is kept in reset.

Write Mode

Data are latched on WR rising edge.

Read Mode

Data are output on D0-D7 bus on RD rising edge. Data Bus is set in high impedance mode when RD is set to

logic 1.

Accordingly to R bit value I2C Address or Status Byte is output on D0-D7 bus.

Figure 49. 8080-series parallel bus protocol - one byte transmission

D/C

R/W

LR0082

D/C

R/W

LR0046

Note 1) Data Bus is configured in high impedence mode after evry RD rising edge

2) Always the same data is output on D0-D7

D/C

LR0083

STE2004DIE2 Datasheet(PDF) 35 Page - STMicroelectronics