2

PS2022A 03/11/96

12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012

PI74FCT646/648/651/652T

(25

Ω

Ω

Ω

Ω

Ω Series) P174FCT2646T/2652T

OCTAL REGISTERED TRANSCEIVERS

Pin Name

Description

Data Register A Inputs

Data Register B Outputs

Data Register B Inputs

Data Register A Outputs

CPAB, CPBA

Clock Pulse Inputs

SAB, SBA

Output Data Source Select Inputs

DIR, G

Output Enable Inputs

(646/648/2646)

GAB, GBA

Output Enable Inputs

(651/652/2652)

GND

Ground

Power

Product Pin Description

PI74FCT646/648T

Product Pin Configuration

PI74FCT651/652T

Product Pin Configuration

PI74FCT646/2646T

PI74FCT648T

Inputs

DATA I/O

(2)

Function/Operation

Function/Operation

G

DIR

CPAB CPBA SAB

SBA

A0-A7

B0-B7

Isolation

Isolation

H

X

H or L

H or L

X

X

Input

Input

Store A and B Data

Store A and B Data

H

X

↑↑

XX

Real Time B Data to A Bus

Real Time B Data to A Bus

L

L

X

X

X

L

Output

Input

Stored B Data to A Bus

Stored B Data to A Bus

L

L

X

H or L

X

H

Real Time A Data to B Bus

Real Time A Data to B Bus

L

H

X

X

L

X

Input

Output

Stored A Data to B Bus

Stored A Data to B Bus

L

H

H or L

X

H

X

PI74FCT646/648/2646T Truth Table

PI74FCT651T

PI74FCT652/2652T

Inputs

DATA I/O

(2)

Function/Operation

Function/Operation

GAB

GBA

CPAB CPBA SAB

SBA

A0-A7

B0-B7

Isolation

Isolation

L

H

H or L

H or L

X

X

Input

Input

Store A and B Data

Store A and B Data

L

H

↑↑

XX

Store A, Hold B

Store A, Hold B

X

H

↑

H or L

X

X

Input

Unspecified

(1)

Store A in Both Registers

(3)

Store A in Both Registers

H

H

↑↑

X

(2)

X

Input

Output

Hold A, Store B

Hold A, Store B

L

X

H or L

↑

XX

Unspecified

(1)

Input

Store B in Both Registers

(4)

Store B in Both Registers

L

L

↑↑

XX

(2)

Output

Input

Real Time B Data to A Bus

Real Time B Data to A Bus

L

L

X

X

X

L

Output

Input

Stored B Data to A Bus

Stored B Data to A Bus

L

L

X

H or L

X

H

Real Time A Data to B Bus

Real Time A Data to B Bus

HHXX

L

X

Input

Output

Stored A Data to B Bus

Stored A Data to B Bus

H

H

H or L

X

H

X

Stored A Data to B Bus and Stored A Data to B Bus and

H

L

H or L

H or L

H

H

Output

Output

Stored B Data to A Bus

Stored B Data to A Bus

PI74FCT651/652/2652T Truth Table

1.

The data output functions may be enabled or disabled by various signals at the GAB or GBA inputs. Data

input functions are always enabled, i.e., data at the bus pins will be stored on every low-to-high transition

on the clock inputs.

2.

Select control = L: clocks can occur simultaneously.

Select control = H: clocks must be staggered in order to load both registers.

3.

A in B Register

4.

B in A Register

1

2

3

4

5

6

7

8

9

10

11

12

24

23

22

21

20

19

18

17

16

15

14

13

CPAB

SAB

DIR

GND

Vcc

CPBA

SBA

G

24-PIN

P24

Q24

R24

S24

1

2

3

4

5

6

7

8

9

10

11

12

24

23

22

21

20

19

18

17

16

15

14

13

CPAB

SAB

GAB

GND

Vcc

CPBA

SBA

GBA

24-PIN

P24

Q24

R24

S24