ADL5306

PIN CONFIGURATION AND PIN FUNCTION DESCRIPTIONS

NC

INPT

VREF

IREF

SCAL

BFIN

COMM

COMM

COMM

VPOS

COMM

VNEG

VNEG

VSUM

VOUT

VLOG

1

2

3

4

56

7

8

9

10

11

12

13

14

15

16

ADL5306

03727-0-002

Figure 2. 16-Lead Leadframe Chip Scale Package (LFCSP)

Table 3. Pin Function Descriptions

Pin No.

Mnemonic

Function

1

NC

N/A

2

VREF

Reference Output Voltage of 2.5 V.

3

IREF

4

INPT

into INPT.

5

VSUM

Guard Pin. Used to shield the INPT current line and for optional adjustment of the INPT and IREF node potential.

6, 7

VNEG

8

VPOS

9

VLOG

Output of the Logarithmic Front End.

10

BFIN

Buffer Amplifier Noninverting Input.

11

SCAL

Buffer Amplifier Inverting Input.

12

VOUT

Buffer Output.

13–16

COMM

Analog Ground.

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