MC68331MFC16 datasheet(56/84 Pages) NXP

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MC68331TS/D

DDRQS determines whether pins are inputs or outputs. Clearing a bit makes the corresponding pin an

input; setting a bit makes the pin an output. DDRQS affects both QSPI function and I/O function.

NOTES:

1. PQS2 is a digital I/O pin unless the SPI is enabled (SPE in SPCR1 set), in which case it becomes SPI serial

clock SCK.

2. PQS7 is a digital I/O pin unless the SCI transmitter is enabled (TE in SCCR1 = 1), in which case it becomes

SCI serial output TXD.

DDRQS determines the direction of the TXD pin only when the SCI transmitter is disabled. When the

SCI transmitter is enabled, the TXD pin is an output.

5.4 QSPI Submodule

The QSPI submodule communicates with external devices through a synchronous serial bus. The QSPI

is fully compatible with the serial peripheral interface (SPI) systems found on other Motorola products.

A block diagram of the QSPI is shown below.

Table 24 Effect of DDRQS on QSM Pin Function

QSM Pin

Mode

DDRQS

Bit

State

Pin Function

MISO

Master

DDQ0

Serial Data Input to QSPI

Disables Data Input

Slave

Disables Data Output

Serial Data Output from QSPI

MOSI

Master

DDQ1

Disables Data Output

Serial Data Output from QSPI

Slave

Serial Data Input to QSPI

Disables Data Input

SCK1

Master

DDQ2

Disables Clock Output

Clock Output from QSPI

Slave

Clock Input to QSPI

Disables Clock Input

PCS0/SS

Master

DDQ3

Assertion Causes Mode Fault

Chip-Select Output

Slave

QSPI Slave Select Input

Disables Select Input

PCS[3:1]

Master

DDQ[4:6

]

Disables Chip-Select Output

Chip-Select Output

Slave

Inactive

TXD2

Transmit

DDQ7

Serial Data Output from SCI

RXD

Receive

None

Serial Data Input to SCI

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

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