8V97053 datasheet(21/57 Pages) RENESAS

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February 2, 2023

8V97053 Datasheet

Phase and Frequency Detector (PFD) and Charge Pump

The phase detector compares the outputs from the R counter and from the N counter and generates an output corresponding to the

phase and frequency difference between the two inputs the PFD. The charge pump current is programmable through the serial port (SPI)

to several different levels.

The PFD offers an anti-backlash function that helps to avoid any dead zone in the PFD transfer function.

Figure 3. Simplified PFD Circuit using D-type Flip-flop

The Band Select logic operates between 125kHz and 500kHz. The Band Select clock divider needs to be set to divide down the PFD

frequency to between 125kHz to 500kHz (logic maximum frequency).

PFD Frequency

The VCO Band Selection can be used while operating at PFD frequencies up to 310MHz.

If the application requires the PFD frequency to be higher than 125MHz, the user can use one of the following two techniques

(Technique A is the recommended procedure):

▪ Technique A – The user can use the ExtBndSelDiv[4:1] bits (Bits[D6:D3]) in Register 6. These additional band select divider bits

extend the band select divider from 8-bits (available in Register 4) to 12-bits. The four additional band select divider bits in Register 4

are the most significant bits of the divide value. For proper VCO band selection, the PFD frequency divided by the band select divide

value must be 500kHz and  125kHz.

▪ Technique B – If choosing this second technique, the user must follow the three following steps:

Disable the Phase Adjust function by setting the bit D28 In Register 1 to 0, keep the PFD frequency lower than 125MHz, and program the

desired VCO frequency.

Enable the phase adjust function by setting BAND_SEL_DISABLE (Bit D28 in Register 1) to 1.

Set the desired PFD frequency and program the relevant

R divider and N counter values.

In either technique, the Lock Detect Precision should be programmed to be lower than the PFD period using the bit [D7] in Register 2 and

the bits [D27:D26] in Register 6 (see Table 11).

VDD

REF_IN x (1+D)/R

CP_OUT

VDD

DELAY

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