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74LVC373APW Datasheet(PDF) 8 Page - NXP Semiconductors |
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74LVC373APW Datasheet(HTML) 8 Page - NXP Semiconductors |
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8 / 12 page ![]() Philips Semiconductors Product specification 74LVC373A Octal D-type transparent latch with 5-volt tolerant inputs/outputs (3-State) 1998 Jul 29 8 AC WAVEFORMS with 5-volt tolerant inputs/outputs VM = 1.5V at VCC w 2.7V; VM = 0.5 VCC at VCC t 2.7V. VOL and VOH are the typical output voltage drop that occur with the output load. VX = VOL + 0.3V at VCC w 2.7V; VX = VOL + 0.1 VCC at VCC t 2.7V VY = VOH –0.3V at VCC w 2.7V; VY = VOH – 0.1 VCC at VCC t 2.7V VM Dn INPUT VM LE INPUT tSU th NOTE: The shaded areas indicate when the input is permitted to change for predictable output performance. SW00073 tSU th VI GND VI GND Waveform 4. Data setup and hold times for the Dn input to the LE input. (The shaded areas indicate when the input is permitted to change for predictable output performance). TEST CIRCUIT PULSE GENERATOR RT VIN D.U.T. VOUT CL VCC RL=500 Ω SWITCH POSITION TEST SWITCH tPLH/tPHL Open tPLZ/tPZL 2 <VCC tPHZ/tPZH GND Test Circuit for 3-State Outputs Open GND S1 2 <VCC DEFINITIONS VCC t 2.7V 2.7 – 3.6V VIN VCC 2.7V RL = Load resistor CL = Load capacitance includes jig and probe capacitance RT = Termination resistance should be equal to ZOUT of pulse generators. SW00047 RL=500 Ω Waveform 5. Load circuitry for switching times. |
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