PIC12CE518 datasheet(13/88 Pages) MICROCHIP

13 / 88 page

Preliminary

DS40172A-page 13

PIC12CE5XX

4.2.2

SPECIAL FUNCTION REGISTERS

The Special Function Registers (SFRs) are registers

used by the CPU and peripheral functions to control

the operation of the device (Table 4-1).

The special registers can be classiﬁed into two sets.

The special function registers associated with the

“core” functions are described in this section. Those

related to the operation of the peripheral features are

described in the section for each peripheral feature.

TABLE 4-1:

SPECIAL FUNCTION REGISTER (SFR) SUMMARY

Address

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1 Bit 0

Value on

Power-On

Reset

Value on

MCLR and

WDT Reset

Value on

Wake-up on

Pin Change

N/A

TRIS

—

I/O control registers

--11 1111

N/A

OPTION

Contains control bits to conﬁgure Timer0, Timer0/WDT

prescaler, wake-up on change, and weak pull-ups

1111 1111

00h

INDF

Uses contents of FSR to address data memory (not a physical

xxxx xxxx

uuuu uuuu

01h

TMR0

8-bit real-time clock/counter

xxxx xxxx

uuuu uuuu

02h(1)

PCL

Low order 8 bits of PC

1111 1111

03h

STATUS

GPWUF

—

PA0

0001 1xxx

000q quuu

100q quuu

04h

FSR

(12CE518) Indirect data memory address pointer

111x xxxx

111u uuuu

04h

FSR

(12CE519) Indirect data memory address pointer

110x xxxx

11uu uuuu

05h

OSCCAL

(12CE518/

12CE519)

CAL7

CAL6 CAL5 CAL4 CALFST CALSLW

—

0111 00--

uuuu uu--

06h

GPIO

SCL

SDA

GP5

GP4

GP3

GP2

GP1 GP0 11xx xxxx

11uu uuuu

Legend: Shaded boxes = unimplemented or unused, — = unimplemented, read as '0' (if applicable)

= unknown, u = unchanged, q = see the tables in Section 8.7 for possible values.

Note 1:

The upper byte of the Program Counter is not directly accessible. See Section 4.6

for an explanation of how to access these bits.

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