PIC12C672 datasheet(39/88 Pages) MICROCHIP

39 / 88 page

Preliminary

DS40172A-page 39

PIC12CE5XX

8.9

Power-Down Mode (SLEEP)

A device may be powered down (SLEEP) and later

powered up (Wake-up from SLEEP).

8.9.1

SLEEP

The Power-Down mode is entered by executing a

SLEEP

instruction.

If enabled, the Watchdog Timer will be cleared but

keeps running, the TO bit (STATUS<4>) is set, the PD

bit (STATUS<3>) is cleared and the oscillator driver is

turned off. The I/O ports maintain the status they had

before the SLEEP instruction was executed (driving

high, driving low, or hi-impedance).

It should be noted that a RESET generated by a WDT

time-out does not drive the MCLR pin low.

For lowest current consumption while powered down,

the T0CKI input should be at VDD or VSS and the GP3/

MCLR/VPP pin must be at a logic high level if MCLR is

enabled.

8.9.2

WAKE-UP FROM SLEEP

The device can wake-up from SLEEP through one of

the following events:

An external reset input on GP3/MCLR/VPP pin,

when conﬁgured as MCLR.

A Watchdog Timer time-out reset (if WDT was

enabled).

A change on input pin GP0, GP1, or GP3/

MCLR/VPP

when

wake-up

change

enabled.

These events cause a device reset. The TO, PD, and

GPWUF bits can be used to determine the cause of

device reset. The TO bit is cleared if a WDT time-out

occurred (and caused wake-up). The PD bit, which is

set on power-up, is cleared when SLEEP is invoked.

The GPWUF bit indicates a change in state while in

SLEEP at pins GP0, GP1, or GP3 (since the last time

there was a ﬁle or bit operation on GP port).

The WDT is cleared when the device wakes from

sleep, regardless of the wake-up source.

Caution: Right before entering SLEEP, read the

input pins. When in SLEEP, wake up

occurs when the values at the pins change

from the state they were in at the last

reading. If a wake-up on change occurs

and

the

pins

are

not

read

before

reentering SLEEP, a wake up will occur

immediately even if no pins change while

in SLEEP mode.

8.10

Program Veriﬁcation/Code Protection

If the code protection bit has not been programmed,

the on-chip program memory can be read out for

veriﬁcation purposes.

The ﬁrst 64 locations can be read regardless of the

code protection bit setting.

Note:

The

location

containing

the

pre-pro-

grammed internal RC oscillator calibration

value is never code protected.

8.11

ID Locations

Four memory locations are designated as ID locations

where the user can store checksum or other code-

identiﬁcation

numbers. These

locations

are

not

accessible during normal execution but are readable

and writable during program/verify.

Use only the lower 4 bits of the ID locations and

always program the upper 8 bits as '0's.

12CF5XX_GEBook Page 39 Tuesday, October 21, 1997 8:23 AM

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