PCF85053A datasheet(21/43 Pages) NXP

21 / 43 page

NXP Semiconductors

PCF85053A

Bootable CPU RTC with two I2C buses, 128 byte SRAM and alarm function

-2

-1

aaa-009637

(3)

(2)

(1)

measured/calculated

deviation 8.51975 ppm

deviation after

correction in

OFFM = 1

+0.382 ppm

deviation after

correction in

OFFM = 0

-0.160 ppm

(1) 4 correction pulses in OFFM = 0 correspond to -8.680 ppm.

(2) 4 correction pulses in OFFM = 1 correspond to -8.138 ppm.

(3) Reachable accuracy zone.

Figure 9. Result of offset calibration

7.8 Oscillator register (13h)

Address

13h

Oscillator

CLKIV

OFFM

LOWJ

OSCD[1:0]

CL[1:0]

Table 32. Oscillator register byte

Address

Primary I2C

2nd I2C

Note

control bit XCLK

XCLK=1

XCLK=0

(default)

XCLK=1

XCLK=0

(default)

Only primary I2C controller

can write “XCLK” bit

13h

Oscillator Register

Read/Write Read only

Read only

Read/Write

For clock calibration

The primary I2C can change

the access capability

(see section Section 7.9)

Table 33. Oscillator register read/write capability configuration

Bit

Symbol

Value

Description

0 (default)

non-inverting; LOWJ mode will affect rising edge

CLKIV

inverted; LOWJ mode will affect falling edge

0 (default)

normal mode: correction is made every 4 hours

OFFM

fast mode: correction is made once every 8 minutes

Rsvd

reserved

0 (default)

normal mode

LOWJ

reduced CLK output jitter; increase IDD

D3-D2

OSCD[1:0]

00 (default)

normal drive; Rs(max)- 100 kΩ

Table 34. Oscillator register bit detail (default value: 00h)

PCF85053A

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Product data sheet

Rev. 1.0 — 31 January 2023

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