 |
Electronic Components Datasheet Search |
|
|
Electronic Components Datasheet Search |
|
89TSF552 Datasheet(PDF) 13 Page - Renesas Technology Corp |
|
|
|||||||||||||||||||||||||||||
89TSF552 Datasheet(HTML) 13 Page - Renesas Technology Corp |
|
|
13 / 39 page  13 of 38 June 17, 2005 IDT 89TSF552 *Notice: The information in this document is subject to change without notice foSDREF Frequency offset between source and target SerDes reference clocks –100 — +100 ppm TRSDREFCI SerDes reference clock input rise time (10% to 90%) —— TBD ns TRZBCI TFSDREFCI SerDes reference clock input fall time (90% to 10%) —— TBD ns TFZBCI Symbol Parameter Min Typical Max Units Notes JDR Deterministic jitter at receiver — — 0.37 UI JTR Total jitter at receiver — — 0.52 UI at 10–12 BER ZRTERM Single-ended termination of differential inputs 45 — 55 Ω LDR Rx return loss TBD — — dB 100 MHz to 1.875 GHz — Rx common mode return loss TBD — — dB 100 MHz to 1.875 GHz VRSense Input sensitivity 200 — — mV Differential peak-peak VMAX Maximum input voltage — — 2000 mV Differential peak-peak Treye “Eye” opening 190 — — ps Iroff Off current –50 — 50 mA Maximum current into a pin with power off Table 21 89TSF552 SerDes Interface Receiver Characteristics Symbol Parameter Min Typical1 1. The typical amplitude values are obtained when VDD_TX=2.5V, and VDD_SD=1.8V Max Units Notes VDIFF1 Differential output (without pre-emphasis) (amplitude setting 1) 430 680 — mV Refer to Table 23. VDIFF2 Differential output (without pre-emphasis) (amplitude setting 2) 660 1100 — mV Refer to Table 24. VDIFF3 Differential output (without pre-emphasis) (amplitude setting 3) 700 1200 — mV Refer to Table 25. tdrf Driver rise/fall time Amplitude Setting 1 — — 240 ps Measured at 20–80% Amplitude Setting 3 — — 270 ps Measured at 20–80% ZD Differential output impedance — 100 — Ω 100 MHz to 1.875 GHz ZSE Single-ended output impedance — 50 — Ω 100 MHz to 1.875 GHz ZMSE Single-ended output impedance matching 3 — 8 % 100 MHz to 1.875 GHz JD Deterministic jitter — — 0.14 UI Without pre-emphasis JT Total jitter — — 0.38 UI At ±7 sigma Table 22 89TSF552 SerDes Interface Transmitter Characteristics Symbol Parameter Min Typical Max Units Conditions Table 20 89TSF552 SerDes Reference Clock Characteristics (Part 2 of 2) |
|
Link URL |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link to Datasheet | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
New Zealand ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
